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hwpmc: Skip GLOBAL_CTRL updates on stop_pmc().

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After we wipe PMC configuration, including its local enable bit(s),
we don't really care about its global enable bit.  Global enable bits
now may only be cleared by interrupt handler in case of error (sample
buffer overflow).  Being set is actually a reset default for them.

This saves one WRMSR per process-scope PMC per context switch, that
is clearly visible in profiles.

MFC after:	1 month
This commit is contained in:
Alexander Motin 2022-06-02 18:20:33 -04:00
parent 04e86ae357
commit 326a8d3e08
2 changed files with 4 additions and 10 deletions
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8
sys/dev/hwpmc/hwpmc_core.c
View file

@ -472,8 +472,7 @@ iaf_stop_pmc(int cpu, int ri)
cc->pc_iafctrl &= ~(IAF_MASK << (ri * 4));
wrmsr(IAF_CTRL, cc->pc_iafctrl);
cc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET));
wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
/* Don't need to write IA_GLOBAL_CTRL, one disable is enough. */
PMCDBG4(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)",
cc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL),
@ -975,10 +974,7 @@ iap_stop_pmc(int cpu, int ri)
wrmsr(IAP_EVSEL0 + ri, 0);
if (core_version >= 2) {
cc->pc_globalctrl &= ~(1ULL << ri);
wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl);
}
/* Don't need to write IA_GLOBAL_CTRL, one disable is enough. */
return (0);
}

6
sys/dev/hwpmc/hwpmc_uncore.c
View file

@ -366,8 +366,7 @@ ucf_stop_pmc(int cpu, int ri)
PMCDBG1(MDP,STO,1,"ucf-stop ucfctrl=%x", ucfc->pc_ucfctrl);
wrmsr(UCF_CTRL, ucfc->pc_ucfctrl);
ucfc->pc_globalctrl &= ~(1ULL << (ri + SELECTOFF(uncore_cputype)));
wrmsr(UC_GLOBAL_CTRL, ucfc->pc_globalctrl);
/* Don't need to write UC_GLOBAL_CTRL, one disable is enough. */
PMCDBG4(MDP,STO,1,"ucfctrl=%x(%x) globalctrl=%jx(%jx)",
ucfc->pc_ucfctrl, (uint32_t) rdmsr(UCF_CTRL),
@ -724,8 +723,7 @@ ucp_stop_pmc(int cpu, int ri)
/* stop hw. */
wrmsr(SELECTSEL(uncore_cputype) + ri, 0);
cc->pc_globalctrl &= ~(1ULL << ri);
wrmsr(UC_GLOBAL_CTRL, cc->pc_globalctrl);
/* Don't need to write UC_GLOBAL_CTRL, one disable is enough. */
return (0);
}