diff --git a/sys/mips/include/_align.h b/sys/mips/include/_align.h
index 4484a28aa0b..f945164d260 100644
--- a/sys/mips/include/_align.h
+++ b/sys/mips/include/_align.h
@@ -44,10 +44,10 @@
 
 /*
  * Round p (pointer or byte index) up to a correctly-aligned value for all
- * data types (int, long, ...).	  The result is u_int and must be cast to
+ * data types (int, long, ...).	  The result is u_long and must be cast to
  * any desired pointer type.
  */
 #define	_ALIGNBYTES	7
-#define	_ALIGN(p)	(((u_int)(p) + _ALIGNBYTES) &~ _ALIGNBYTES)
+#define	_ALIGN(p)	(((u_long)(p) + _ALIGNBYTES) &~ _ALIGNBYTES)
 
 #endif /* !_MIPS_INCLUDE__ALIGN_H_ */
diff --git a/sys/mips/include/_bus.h b/sys/mips/include/_bus.h
index 74865da17db..54b0cbb6563 100644
--- a/sys/mips/include/_bus.h
+++ b/sys/mips/include/_bus.h
@@ -31,19 +31,20 @@
 
 #ifndef MIPS_INCLUDE__BUS_H
 #define	MIPS_INCLUDE__BUS_H
-#ifdef TARGET_OCTEON
-#include "_bus_octeon.h"
-#else
 /*
  * Bus address and size types
  */
+#include "opt_cputype.h" 
+#if !(defined(TARGET_OCTEON) && defined(ISA_MIPS32))
 typedef uintptr_t bus_addr_t;
+#else
+typedef uint64_t bus_addr_t;
+#endif
 typedef uintptr_t bus_size_t;
 
 /*
  * Access methods for bus resources and address space.
  */
-typedef long bus_space_tag_t;
-typedef u_long bus_space_handle_t;
-#endif
+typedef struct bus_space *bus_space_tag_t;
+typedef bus_addr_t bus_space_handle_t;
 #endif /* MIPS_INCLUDE__BUS_H */
diff --git a/sys/mips/include/_types.h b/sys/mips/include/_types.h
index ec94439f40c..1fd760f9cb5 100644
--- a/sys/mips/include/_types.h
+++ b/sys/mips/include/_types.h
@@ -54,7 +54,7 @@ typedef	unsigned short		__uint16_t;
 typedef	int			__int32_t;
 typedef	unsigned int		__uint32_t;
 
-#ifdef __mips64
+#ifdef __mips_n64
 typedef	long			__int64_t;
 typedef	unsigned long		__uint64_t;
 #else
@@ -79,14 +79,14 @@ typedef	unsigned long long	__uint64_t;
  */
 typedef	__int32_t	__clock_t;		/* clock()... */
 typedef	unsigned int	__cpumask_t;
-#ifdef __mips64
+#ifdef __mips_n64
 typedef	__int64_t	__critical_t;
 #else
 typedef	__int32_t	__critical_t;
 #endif
 typedef	double		__double_t;
 typedef	double		__float_t;
-#ifdef __mips64
+#ifdef __mips_n64
 typedef	__int64_t	__intfptr_t;
 typedef	__int64_t	__intptr_t;
 #else
@@ -102,14 +102,14 @@ typedef	__int8_t	__int_least8_t;
 typedef	__int16_t	__int_least16_t;
 typedef	__int32_t	__int_least32_t;
 typedef	__int64_t	__int_least64_t;
-#if defined(__mips64) || defined(ISA_MIPS64)
+#if defined(__mips_n64) || defined(__mips_n32)
 typedef	__int64_t	__register_t;
 typedef	__int64_t	f_register_t;
 #else
 typedef	__int32_t	__register_t;
 typedef	__int32_t	f_register_t;
 #endif
-#ifdef __mips64
+#ifdef __mips_n64
 typedef	__int64_t	__ptrdiff_t;
 typedef	__int64_t	__segsz_t;
 typedef	__uint64_t	__size_t;
@@ -134,13 +134,16 @@ typedef	__uint8_t	__uint_least8_t;
 typedef	__uint16_t	__uint_least16_t;
 typedef	__uint32_t	__uint_least32_t;
 typedef	__uint64_t	__uint_least64_t;
-#if defined(__mips64) || defined(ISA_MIPS64)
+#if defined(__mips_n64) || defined(__mips_n32)
 typedef	__uint64_t	__u_register_t;
+#else
+typedef	__uint32_t	__u_register_t;
+#endif
+#if defined(__mips_n64)
 typedef	__uint64_t	__vm_offset_t;
 typedef	__uint64_t	__vm_paddr_t;
 typedef	__uint64_t	__vm_size_t;
 #else
-typedef	__uint32_t	__u_register_t;
 typedef	__uint32_t	__vm_offset_t;
 typedef	__uint32_t	__vm_paddr_t;
 typedef	__uint32_t	__vm_size_t;
@@ -162,8 +165,4 @@ typedef	char *			__va_list;
 typedef __va_list		__gnuc_va_list;	/* compatibility w/GNU headers*/
 #endif
 
-typedef struct label_t {
-	__register_t val[13];
-} label_t;
-
 #endif /* !_MACHINE__TYPES_H_ */
diff --git a/sys/mips/include/asm.h b/sys/mips/include/asm.h
index 0df221e26d5..db6929d0d9b 100644
--- a/sys/mips/include/asm.h
+++ b/sys/mips/include/asm.h
@@ -60,6 +60,7 @@
 #include <machine/regdef.h>
 #endif
 #include <machine/endian.h>
+#include <machine/cdefs.h>
 
 #undef __FBSDID
 #if !defined(lint) && !defined(STRIP_FBSDID)
@@ -281,7 +282,7 @@ _C_LABEL(x):
  * Macros to panic and printf from assembly language.
  */
 #define	PANIC(msg)			\
-	la	a0, 9f;			\
+	PTR_LA	a0, 9f;			\
 	jal	_C_LABEL(panic);	\
 	nop;				\
 	MSG(msg)
@@ -289,7 +290,7 @@ _C_LABEL(x):
 #define	PANIC_KSEG0(msg, reg)	PANIC(msg)
 
 #define	PRINTF(msg)			\
-	la	a0, 9f;			\
+	PTR_LA	a0, 9f;			\
 	jal	_C_LABEL(printf);	\
 	nop;				\
 	MSG(msg)
@@ -308,23 +309,24 @@ _C_LABEL(x):
  */
 #define DO_AST				             \
 44:				                     \
-	la	s0, _C_LABEL(disableintr)           ;\
+	PTR_LA	s0, _C_LABEL(disableintr)           ;\
 	jalr	s0                                  ;\
 	nop                                         ;\
+	move	a0, v0                              ;\
 	GET_CPU_PCPU(s1)                            ;\
 	lw	s3, PC_CURPCB(s1)                   ;\
 	lw	s1, PC_CURTHREAD(s1)                ;\
 	lw	s2, TD_FLAGS(s1)                    ;\
 	li	s0, TDF_ASTPENDING | TDF_NEEDRESCHED;\
 	and	s2, s0                              ;\
-	la	s0, _C_LABEL(enableintr)            ;\
+	PTR_LA	s0, _C_LABEL(restoreintr)           ;\
 	jalr	s0                                  ;\
 	nop                                         ;\
 	beq	s2, zero, 4f                        ;\
 	nop                                         ;\
-	la	s0, _C_LABEL(ast)                   ;\
+	PTR_LA	s0, _C_LABEL(ast)                   ;\
 	jalr	s0                                  ;\
-	addu	a0, s3, U_PCB_REGS                  ;\
+	PTR_ADDU a0, s3, U_PCB_REGS                 ;\
 	j 44b			                    ;\
         nop                                         ;\
 4:
@@ -361,12 +363,15 @@ _C_LABEL(x):
  */
 
 #if !defined(_MIPS_BSD_API) || _MIPS_BSD_API == _MIPS_BSD_API_LP32
+/* #if !defined(__mips_n64) */
 #define	REG_L		lw
 #define	REG_S		sw
 #define	REG_LI		li
 #define	REG_PROLOGUE	.set push
 #define	REG_EPILOGUE	.set pop
 #define	SZREG		4
+#define	PTR_LA		la
+#define	PTR_ADDU	addu
 #else
 #define	REG_L		ld
 #define	REG_S		sd
@@ -374,6 +379,8 @@ _C_LABEL(x):
 #define	REG_PROLOGUE	.set push ; .set mips3
 #define	REG_EPILOGUE	.set pop
 #define	SZREG		8
+#define	PTR_LA		dla
+#define	PTR_ADDU	daddu
 #endif	/* _MIPS_BSD_API */
 
 #define	mfc0_macro(data, spr)						\
diff --git a/sys/mips/include/atomic.h b/sys/mips/include/atomic.h
index 9f800cd1d21..4b87738cf90 100644
--- a/sys/mips/include/atomic.h
+++ b/sys/mips/include/atomic.h
@@ -34,6 +34,17 @@
 #error this file needs sys/cdefs.h as a prerequisite
 #endif
 
+/*
+ * Note: All the 64-bit atomic operations are only atomic when running
+ * in 64-bit mode.  It is assumed that code compiled for n32 and n64
+ * fits into this definition and no further safeties are needed.
+ *
+ * It is also assumed that the add, subtract and other arithmetic is
+ * done on numbers not pointers.  The special rules for n32 pointers
+ * do not have atomic operations defined for them, but generally shouldn't
+ * need atomic operations.
+ */
+
 static __inline  void
 mips_sync(void)
 {
@@ -126,7 +137,7 @@ atomic_subtract_32(__volatile uint32_t *p, uint32_t v)
 		"1:\tll	%0, %3\n\t"		/* load old value */
 		"subu	%0, %2\n\t"		/* calculate new value */
 		"sc	%0, %1\n\t"		/* attempt to store */
-		"beqz	%0, 1b\n\t"			/* spin if failed */
+		"beqz	%0, 1b\n\t"		/* spin if failed */
 		: "=&r" (temp), "=m" (*p)
 		: "r" (v), "m" (*p)
 		: "memory");
@@ -166,6 +177,110 @@ atomic_readandset_32(__volatile uint32_t *addr, uint32_t value)
 	return result;
 }
 
+#if defined(__mips_n64) || defined(__mips_n32)
+static __inline void
+atomic_set_64(__volatile uint64_t *p, uint64_t v)
+{
+	uint64_t temp;
+
+	__asm __volatile (
+		"1:\n\t"
+		"lld	%0, %3\n\t"		/* load old value */
+		"or	%0, %2, %0\n\t"		/* calculate new value */
+		"scd	%0, %1\n\t"		/* attempt to store */
+		"beqz	%0, 1b\n\t"		/* spin if failed */
+		: "=&r" (temp), "=m" (*p)
+		: "r" (v), "m" (*p)
+		: "memory");
+
+}
+
+static __inline void
+atomic_clear_64(__volatile uint64_t *p, uint64_t v)
+{
+	uint64_t temp;
+	v = ~v;
+
+	__asm __volatile (
+		"1:\n\t"
+		"lld	%0, %3\n\t"		/* load old value */
+		"and	%0, %2, %0\n\t"		/* calculate new value */
+		"scd	%0, %1\n\t"		/* attempt to store */
+		"beqz	%0, 1b\n\t"		/* spin if failed */
+		: "=&r" (temp), "=m" (*p)
+		: "r" (v), "m" (*p)
+		: "memory");
+}
+
+static __inline void
+atomic_add_64(__volatile uint64_t *p, uint64_t v)
+{
+	uint64_t temp;
+
+	__asm __volatile (
+		"1:\n\t"
+		"lld	%0, %3\n\t"		/* load old value */
+		"daddu	%0, %2, %0\n\t"		/* calculate new value */
+		"scd	%0, %1\n\t"		/* attempt to store */
+		"beqz	%0, 1b\n\t"		/* spin if failed */
+		: "=&r" (temp), "=m" (*p)
+		: "r" (v), "m" (*p)
+		: "memory");
+}
+
+static __inline void
+atomic_subtract_64(__volatile uint64_t *p, uint64_t v)
+{
+	uint64_t temp;
+
+	__asm __volatile (
+		"1:\n\t"
+		"lld	%0, %3\n\t"		/* load old value */
+		"dsubu	%0, %2\n\t"		/* calculate new value */
+		"scd	%0, %1\n\t"		/* attempt to store */
+		"beqz	%0, 1b\n\t"		/* spin if failed */
+		: "=&r" (temp), "=m" (*p)
+		: "r" (v), "m" (*p)
+		: "memory");
+}
+
+static __inline uint64_t
+atomic_readandclear_64(__volatile uint64_t *addr)
+{
+	uint64_t result,temp;
+
+	__asm __volatile (
+		"1:\n\t"
+		"lld	 %0, %3\n\t"		/* load old value */
+		"li	 %1, 0\n\t"		/* value to store */
+		"scd	 %1, %2\n\t"		/* attempt to store */
+		"beqz	 %1, 1b\n\t"		/* if the store failed, spin */
+		: "=&r"(result), "=&r"(temp), "=m" (*addr)
+		: "m" (*addr)
+		: "memory");
+
+	return result;
+}
+
+static __inline uint64_t
+atomic_readandset_64(__volatile uint64_t *addr, uint64_t value)
+{
+	uint64_t result,temp;
+
+	__asm __volatile (
+		"1:\n\t"
+		"lld	 %0,%3\n\t"		/* Load old value*/
+		"or      %1,$0,%4\n\t"
+		"scd	 %1,%2\n\t"		/* attempt to store */
+		"beqz	 %1, 1b\n\t"		/* if the store failed, spin */
+		: "=&r"(result), "=&r"(temp), "=m" (*addr)
+		: "m" (*addr), "r" (value)
+		: "memory");
+
+	return result;
+}
+#endif
+
 #define	ATOMIC_ACQ_REL(NAME, WIDTH)					\
 static __inline  void							\
 atomic_##NAME##_acq_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\
@@ -194,7 +309,7 @@ ATOMIC_ACQ_REL(set, 32)
 ATOMIC_ACQ_REL(clear, 32)
 ATOMIC_ACQ_REL(add, 32)
 ATOMIC_ACQ_REL(subtract, 32)
-#if 0
+#if defined(__mips_n64) || defined(__mips_n32)
 ATOMIC_ACQ_REL(set, 64)
 ATOMIC_ACQ_REL(clear, 64)
 ATOMIC_ACQ_REL(add, 64)
@@ -226,8 +341,22 @@ atomic_store_rel_##WIDTH(__volatile uint##WIDTH##_t *p, uint##WIDTH##_t v)\
 
 ATOMIC_STORE_LOAD(32)
 ATOMIC_STORE_LOAD(64)
-void atomic_store_64 (__volatile uint64_t *, uint64_t *);
-void atomic_load_64 (__volatile uint64_t *, uint64_t *);
+#if !defined(__mips_n64) && !defined(__mips_n32)
+void atomic_store_64(__volatile uint64_t *, uint64_t *);
+void atomic_load_64(__volatile uint64_t *, uint64_t *);
+#else
+static __inline void
+atomic_store_64(__volatile uint64_t *p, uint64_t *v)
+{
+	*p = *v;
+}
+
+static __inline void
+atomic_load_64(__volatile uint64_t *p, uint64_t *v)
+{
+	*v = *p;
+}
+#endif
 
 #undef ATOMIC_STORE_LOAD
 
@@ -294,11 +423,83 @@ atomic_fetchadd_32(__volatile uint32_t *p, uint32_t v)
 		"addu %2, %3, %0\n\t"		/* calculate new value */
 		"sc %2, %1\n\t"			/* attempt to store */
 		"beqz %2, 1b\n\t"		/* spin if failed */
-		: "=&r" (value), "=m" (*p), "=r" (temp)
+		: "=&r" (value), "=m" (*p), "=&r" (temp)
 		: "r" (v), "m" (*p));
 	return (value);
 }
 
+#if defined(__mips_n64) || defined(__mips_n32)
+/*
+ * Atomically compare the value stored at *p with cmpval and if the
+ * two values are equal, update the value of *p with newval. Returns
+ * zero if the compare failed, nonzero otherwise.
+ */
+static __inline uint64_t
+atomic_cmpset_64(__volatile uint64_t* p, uint64_t cmpval, uint64_t newval)
+{
+	uint64_t ret;
+
+	__asm __volatile (
+		"1:\n\t"
+		"lld	%0, %4\n\t"		/* load old value */
+		"bne	%0, %2, 2f\n\t"		/* compare */
+		"move	%0, %3\n\t"		/* value to store */
+		"scd	%0, %1\n\t"		/* attempt to store */
+		"beqz	%0, 1b\n\t"		/* if it failed, spin */
+		"j	3f\n\t"
+		"2:\n\t"
+		"li	%0, 0\n\t"
+		"3:\n"
+		: "=&r" (ret), "=m" (*p)
+		: "r" (cmpval), "r" (newval), "m" (*p)
+		: "memory");
+
+	return ret;
+}
+
+/*
+ * Atomically compare the value stored at *p with cmpval and if the
+ * two values are equal, update the value of *p with newval. Returns
+ * zero if the compare failed, nonzero otherwise.
+ */
+static __inline uint64_t
+atomic_cmpset_acq_64(__volatile uint64_t *p, uint64_t cmpval, uint64_t newval)
+{
+	int retval;
+
+	retval = atomic_cmpset_64(p, cmpval, newval);
+	mips_sync();
+	return (retval);
+}
+
+static __inline uint64_t
+atomic_cmpset_rel_64(__volatile uint64_t *p, uint64_t cmpval, uint64_t newval)
+{
+	mips_sync();
+	return (atomic_cmpset_64(p, cmpval, newval));
+}
+
+/*
+ * Atomically add the value of v to the integer pointed to by p and return
+ * the previous value of *p.
+ */
+static __inline uint64_t
+atomic_fetchadd_64(__volatile uint64_t *p, uint64_t v)
+{
+	uint64_t value, temp;
+
+	__asm __volatile (
+		"1:\n\t"
+		"lld	%0, %1\n\t"		/* load old value */
+		"daddu	%2, %3, %0\n\t"		/* calculate new value */
+		"scd	%2, %1\n\t"		/* attempt to store */
+		"beqz	%2, 1b\n\t"		/* spin if failed */
+		: "=&r" (value), "=m" (*p), "=&r" (temp)
+		: "r" (v), "m" (*p));
+	return (value);
+}
+#endif
+
 /* Operations on chars. */
 #define	atomic_set_char		atomic_set_8
 #define	atomic_set_acq_char	atomic_set_acq_8
@@ -349,7 +550,13 @@ atomic_fetchadd_32(__volatile uint32_t *p, uint32_t v)
 #define	atomic_readandset_int	atomic_readandset_32
 #define	atomic_fetchadd_int	atomic_fetchadd_32
 
-#ifdef __mips64
+/*
+ * I think the following is right, even for n32.  For n32 the pointers
+ * are still 32-bits, so we need to operate on them as 32-bit quantities,
+ * even though they are sign extended in operation.  For longs, there's
+ * no question because they are always 32-bits.
+ */
+#ifdef __mips_n64
 /* Operations on longs. */
 #define	atomic_set_long		atomic_set_64
 #define	atomic_set_acq_long	atomic_set_acq_64
@@ -371,27 +578,7 @@ atomic_fetchadd_32(__volatile uint32_t *p, uint32_t v)
 #define	atomic_fetchadd_long	atomic_fetchadd_64
 #define	atomic_readandclear_long	atomic_readandclear_64
 
-/* Operations on pointers. */
-#define	atomic_set_ptr		atomic_set_64
-#define	atomic_set_acq_ptr	atomic_set_acq_64
-#define	atomic_set_rel_ptr	atomic_set_rel_64
-#define	atomic_clear_ptr	atomic_clear_64
-#define	atomic_clear_acq_ptr	atomic_clear_acq_64
-#define	atomic_clear_rel_ptr	atomic_clear_rel_64
-#define	atomic_add_ptr		atomic_add_64
-#define	atomic_add_acq_ptr	atomic_add_acq_64
-#define	atomic_add_rel_ptr	atomic_add_rel_64
-#define	atomic_subtract_ptr	atomic_subtract_64
-#define	atomic_subtract_acq_ptr	atomic_subtract_acq_64
-#define	atomic_subtract_rel_ptr	atomic_subtract_rel_64
-#define	atomic_cmpset_ptr	atomic_cmpset_64
-#define	atomic_cmpset_acq_ptr	atomic_cmpset_acq_64
-#define	atomic_cmpset_rel_ptr	atomic_cmpset_rel_64
-#define	atomic_load_acq_ptr	atomic_load_acq_64
-#define	atomic_store_rel_ptr	atomic_store_rel_64
-#define	atomic_readandclear_ptr	atomic_readandclear_64
-
-#else /* __mips64 */
+#else /* !__mips_n64 */
 
 /* Operations on longs. */
 #define	atomic_set_long		atomic_set_32
@@ -421,25 +608,26 @@ atomic_fetchadd_32(__volatile uint32_t *p, uint32_t v)
 	atomic_fetchadd_32((volatile u_int *)(p), (u_int)(v))
 #define	atomic_readandclear_long	atomic_readandclear_32
 
+#endif /* __mips_n64 */
+
 /* Operations on pointers. */
-#define	atomic_set_ptr		atomic_set_32
-#define	atomic_set_acq_ptr	atomic_set_acq_32
-#define	atomic_set_rel_ptr	atomic_set_rel_32
-#define	atomic_clear_ptr	atomic_clear_32
-#define	atomic_clear_acq_ptr	atomic_clear_acq_32
-#define	atomic_clear_rel_ptr	atomic_clear_rel_32
-#define	atomic_add_ptr		atomic_add_32
-#define	atomic_add_acq_ptr	atomic_add_acq_32
-#define	atomic_add_rel_ptr	atomic_add_rel_32
-#define	atomic_subtract_ptr	atomic_subtract_32
-#define	atomic_subtract_acq_ptr	atomic_subtract_acq_32
-#define	atomic_subtract_rel_ptr	atomic_subtract_rel_32
-#define	atomic_cmpset_ptr	atomic_cmpset_32
-#define	atomic_cmpset_acq_ptr	atomic_cmpset_acq_32
-#define	atomic_cmpset_rel_ptr	atomic_cmpset_rel_32
-#define	atomic_load_acq_ptr	atomic_load_acq_32
-#define	atomic_store_rel_ptr	atomic_store_rel_32
-#define	atomic_readandclear_ptr	atomic_readandclear_32
-#endif /* __mips64 */
+#define	atomic_set_ptr		atomic_set_long
+#define	atomic_set_acq_ptr	atomic_set_acq_long
+#define	atomic_set_rel_ptr	atomic_set_rel_long
+#define	atomic_clear_ptr	atomic_clear_long
+#define	atomic_clear_acq_ptr	atomic_clear_acq_long
+#define	atomic_clear_rel_ptr	atomic_clear_rel_long
+#define	atomic_add_ptr		atomic_add_long
+#define	atomic_add_acq_ptr	atomic_add_acq_long
+#define	atomic_add_rel_ptr	atomic_add_rel_long
+#define	atomic_subtract_ptr	atomic_subtract_long
+#define	atomic_subtract_acq_ptr	atomic_subtract_acq_long
+#define	atomic_subtract_rel_ptr	atomic_subtract_rel_long
+#define	atomic_cmpset_ptr	atomic_cmpset_long
+#define	atomic_cmpset_acq_ptr	atomic_cmpset_acq_long
+#define	atomic_cmpset_rel_ptr	atomic_cmpset_rel_long
+#define	atomic_load_acq_ptr	atomic_load_acq_long
+#define	atomic_store_rel_ptr	atomic_store_rel_long
+#define	atomic_readandclear_ptr	atomic_readandclear_long
 
 #endif /* ! _MACHINE_ATOMIC_H_ */
diff --git a/sys/mips/include/bus.h b/sys/mips/include/bus.h
index 92557d7cbd3..63b295d2a80 100644
--- a/sys/mips/include/bus.h
+++ b/sys/mips/include/bus.h
@@ -1,8 +1,7 @@
-/*      $NetBSD: bus.h,v 1.12 1997/10/01 08:25:15 fvdl Exp $    */
+/*	$NetBSD: bus.h,v 1.11 2003/07/28 17:35:54 thorpej Exp $	*/
+
 /*-
- * $Id: bus.h,v 1.6 2007/08/09 11:23:32 katta Exp $
- *
- * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
+ * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
  * All rights reserved.
  *
  * This code is derived from software contributed to The NetBSD Foundation
@@ -38,7 +37,7 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-/*
+/*-
  * Copyright (c) 1996 Charles M. Hannum.  All rights reserved.
  * Copyright (c) 1996 Christopher G. Demetriou.  All rights reserved.
  *
diff --git a/sys/mips/include/cache.h b/sys/mips/include/cache.h
index 8f22cdb381a..d73daa211d1 100644
--- a/sys/mips/include/cache.h
+++ b/sys/mips/include/cache.h
@@ -37,6 +37,9 @@
  * $FreeBSD$
  */
 
+#ifndef	_MACHINE_CACHE_H_
+#define	_MACHINE_CACHE_H_
+
 /*
  * Cache operations.
  *
@@ -156,50 +159,8 @@ struct mips_cache_ops {
 extern struct mips_cache_ops mips_cache_ops;
 
 /* PRIMARY CACHE VARIABLES */
-extern u_int mips_picache_size;
-extern u_int mips_picache_line_size;
-extern u_int mips_picache_ways;
-extern u_int mips_picache_way_size;
-extern u_int mips_picache_way_mask;
-
-extern u_int mips_pdcache_size;		/* and unified */
-extern u_int mips_pdcache_line_size;
-extern u_int mips_pdcache_ways;
-extern u_int mips_pdcache_way_size;
-extern u_int mips_pdcache_way_mask;
-extern int mips_pdcache_write_through;
-
-extern int mips_pcache_unified;
-
-/* SECONDARY CACHE VARIABLES */
-extern u_int mips_sicache_size;
-extern u_int mips_sicache_line_size;
-extern u_int mips_sicache_ways;
-extern u_int mips_sicache_way_size;
-extern u_int mips_sicache_way_mask;
-
-extern u_int mips_sdcache_size;		/* and unified */
-extern u_int mips_sdcache_line_size;
-extern u_int mips_sdcache_ways;
-extern u_int mips_sdcache_way_size;
-extern u_int mips_sdcache_way_mask;
-extern int mips_sdcache_write_through;
-
-extern int mips_scache_unified;
-
-/* TERTIARY CACHE VARIABLES */
-extern u_int mips_tcache_size;		/* always unified */
-extern u_int mips_tcache_line_size;
-extern u_int mips_tcache_ways;
-extern u_int mips_tcache_way_size;
-extern u_int mips_tcache_way_mask;
-extern int mips_tcache_write_through;
-
-extern u_int mips_dcache_align;
-extern u_int mips_dcache_align_mask;
-
-extern u_int mips_cache_alias_mask;
-extern u_int mips_cache_prefer_mask;
+extern int mips_picache_linesize;
+extern int mips_pdcache_linesize;
 
 #define	__mco_noargs(prefix, x)						\
 do {									\
@@ -259,3 +220,4 @@ void    mips_config_cache(struct mips_cpuinfo *);
 void    mips_dcache_compute_align(void);
 
 #include <machine/cache_mipsNN.h>
+#endif	/* _MACHINE_CACHE_H_ */
diff --git a/sys/mips/include/cache_mipsNN.h b/sys/mips/include/cache_mipsNN.h
index e44746a2523..9933e74b452 100644
--- a/sys/mips/include/cache_mipsNN.h
+++ b/sys/mips/include/cache_mipsNN.h
@@ -36,6 +36,8 @@
  *
  * $FreeBSD$
  */
+#ifndef	_MACHINE_CACHE_MIPSNN_H_
+#define	_MACHINE_CACHE_MIPSNN_H_
 
 void	mipsNN_cache_init(struct mips_cpuinfo *);
 
@@ -65,3 +67,5 @@ void	mipsNN_pdcache_wbinv_range_index_128(vm_offset_t, vm_size_t);
 void	mipsNN_pdcache_inv_range_128(vm_offset_t, vm_size_t);
 void	mipsNN_pdcache_wb_range_128(vm_offset_t, vm_size_t);
 #endif
+
+#endif	/* _MACHINE_CACHE_MIPSNN_H_ */
diff --git a/sys/mips/include/cpu.h b/sys/mips/include/cpu.h
index 20b41e2a027..3e939a04d7c 100644
--- a/sys/mips/include/cpu.h
+++ b/sys/mips/include/cpu.h
@@ -56,21 +56,30 @@
 #define	MIPS_RESERVED_ADDR		0xbfc80000
 
 #define MIPS_KSEG0_LARGEST_PHYS         0x20000000
-#define	MIPS_CACHED_TO_PHYS(x)		((unsigned)(x) & 0x1fffffff)
-#define	MIPS_PHYS_TO_CACHED(x)		((unsigned)(x) | MIPS_CACHED_MEMORY_ADDR)
-#define	MIPS_UNCACHED_TO_PHYS(x)	((unsigned)(x) & 0x1fffffff)
-#define	MIPS_PHYS_TO_UNCACHED(x)	((unsigned)(x) | MIPS_UNCACHED_MEMORY_ADDR)
+#define	MIPS_CACHED_TO_PHYS(x)		((uintptr_t)(x) & 0x1fffffff)
+#define	MIPS_PHYS_TO_CACHED(x)		((uintptr_t)(x) | MIPS_CACHED_MEMORY_ADDR)
+#define	MIPS_UNCACHED_TO_PHYS(x)	((uintptr_t)(x) & 0x1fffffff)
+#define	MIPS_PHYS_TO_UNCACHED(x)	((uintptr_t)(x) | MIPS_UNCACHED_MEMORY_ADDR)
 
 #define	MIPS_PHYS_MASK			(0x1fffffff)
 #define	MIPS_PA_2_K1VA(x)		(MIPS_KSEG1_START | ((x) & MIPS_PHYS_MASK))
 
-#define	MIPS_VA_TO_CINDEX(x)		((unsigned)(x) & 0xffffff | MIPS_CACHED_MEMORY_ADDR)
+#define	MIPS_VA_TO_CINDEX(x)		((uintptr_t)(x) & 0xffffff | MIPS_CACHED_MEMORY_ADDR)
 #define	MIPS_CACHED_TO_UNCACHED(x)	(MIPS_PHYS_TO_UNCACHED(MIPS_CACHED_TO_PHYS(x)))
 
-#define	MIPS_PHYS_TO_KSEG0(x)		((unsigned)(x) | MIPS_KSEG0_START)
-#define	MIPS_PHYS_TO_KSEG1(x)		((unsigned)(x) | MIPS_KSEG1_START)
-#define	MIPS_KSEG0_TO_PHYS(x)		((unsigned)(x) & MIPS_PHYS_MASK)
-#define	MIPS_KSEG1_TO_PHYS(x)		((unsigned)(x) & MIPS_PHYS_MASK)
+#define	MIPS_PHYS_TO_KSEG0(x)		((uintptr_t)(x) | MIPS_KSEG0_START)
+#define	MIPS_PHYS_TO_KSEG1(x)		((uintptr_t)(x) | MIPS_KSEG1_START)
+#define	MIPS_KSEG0_TO_PHYS(x)		((uintptr_t)(x) & MIPS_PHYS_MASK)
+#define	MIPS_KSEG1_TO_PHYS(x)		((uintptr_t)(x) & MIPS_PHYS_MASK)
+
+#define	MIPS_IS_KSEG0_ADDR(x)					\
+	(((vm_offset_t)(x) >= MIPS_KSEG0_START) &&		\
+	    ((vm_offset_t)(x) <= MIPS_KSEG0_END))
+#define	MIPS_IS_KSEG1_ADDR(x)					\
+	(((vm_offset_t)(x) >= MIPS_KSEG1_START) &&		\
+	    ((vm_offset_t)(x) <= MIPS_KSEG1_END))
+#define	MIPS_IS_VALID_PTR(x)		(MIPS_IS_KSEG0_ADDR(x) || \
+						MIPS_IS_KSEG1_ADDR(x))
 
 /*
  *  Status register.
@@ -154,7 +163,11 @@
  * The bits in the CONFIG register
  */
 #define CFG_K0_UNCACHED	2
+#if defined(CPU_SB1)
+#define CFG_K0_COHERENT	5	/* cacheable coherent */
+#else
 #define	CFG_K0_CACHED	3
+#endif
 
 /*
  * The bits in the context register.
diff --git a/sys/mips/include/cpufunc.h b/sys/mips/include/cpufunc.h
index f3aa5a4c120..cd4d3e5e695 100644
--- a/sys/mips/include/cpufunc.h
+++ b/sys/mips/include/cpufunc.h
@@ -183,20 +183,46 @@ mips_wr_ ## n (uint32_t a0)					\
 	mips_barrier();						\
 } struct __hack
 
+#define	MIPS_RDRW32_COP0_SEL(n,r,s)					\
+static __inline uint32_t					\
+mips_rd_ ## n ## s(void)						\
+{								\
+	int v0;							\
+	__asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";"	\
+			  : [v0] "=&r"(v0));			\
+	mips_barrier();						\
+	return (v0);						\
+}								\
+static __inline void						\
+mips_wr_ ## n ## s(uint32_t a0)					\
+{								\
+	__asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";"	\
+			 __XSTRING(COP0_SYNC)";"		\
+			 "nop;"					\
+			 "nop;"					\
+			 :					\
+			 : [a0] "r"(a0));			\
+	mips_barrier();						\
+} struct __hack
+
 #ifdef TARGET_OCTEON
 static __inline void mips_sync_icache (void)
 {
-    __asm __volatile (
-        ".set mips64\n"
-        ".word 0x041f0000\n"
-        "nop\n"
-        ".set mips0\n"
-        : : );
+	__asm __volatile (
+		".set push\n"
+		".set mips64\n"
+		".word 0x041f0000\n"		/* xxx ICACHE */
+		"nop\n"
+		".set pop\n"
+		: : );
 }
 #endif
 
 MIPS_RDRW32_COP0(compare, MIPS_COP_0_COMPARE);
 MIPS_RDRW32_COP0(config, MIPS_COP_0_CONFIG);
+MIPS_RDRW32_COP0_SEL(config, MIPS_COP_0_CONFIG, 1);
+MIPS_RDRW32_COP0_SEL(config, MIPS_COP_0_CONFIG, 2);
+MIPS_RDRW32_COP0_SEL(config, MIPS_COP_0_CONFIG, 3);
 MIPS_RDRW32_COP0(count, MIPS_COP_0_COUNT);
 MIPS_RDRW32_COP0(index, MIPS_COP_0_TLB_INDEX);
 MIPS_RDRW32_COP0(wired, MIPS_COP_0_TLB_WIRED);
@@ -211,18 +237,13 @@ MIPS_RDRW32_COP0(entryhi, MIPS_COP_0_TLB_HI);
 MIPS_RDRW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
 MIPS_RDRW32_COP0(prid, MIPS_COP_0_PRID);
 MIPS_RDRW32_COP0(watchlo, MIPS_COP_0_WATCH_LO);
+MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 1);
+MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 2);
+MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 3);
 MIPS_RDRW32_COP0(watchhi, MIPS_COP_0_WATCH_HI);
-
-static __inline uint32_t
-mips_rd_config_sel1(void)
-{
-	int v0;
-	__asm __volatile("mfc0 %[v0], $16, 1 ;"
-			 : [v0] "=&r" (v0));
-	mips_barrier();
-	return (v0);
-}
-
+MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 1);
+MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 2);
+MIPS_RDRW32_COP0_SEL(watchhi, MIPS_COP_0_WATCH_HI, 3);
 #undef	MIPS_RDRW32_COP0
 
 static __inline register_t
diff --git a/sys/mips/include/cpuinfo.h b/sys/mips/include/cpuinfo.h
index bf3208626d3..4378c6af2f2 100644
--- a/sys/mips/include/cpuinfo.h
+++ b/sys/mips/include/cpuinfo.h
@@ -57,11 +57,11 @@ struct mips_cpuinfo {
 	u_int16_t	tlb_nentries;
 	u_int8_t	icache_virtual;
 	struct {
-		u_int8_t	ic_size;
+		u_int32_t	ic_size;
 		u_int8_t	ic_linesize;
 		u_int8_t	ic_nways;
 		u_int16_t	ic_nsets;
-		u_int8_t	dc_size;
+		u_int32_t	dc_size;
 		u_int8_t	dc_linesize;
 		u_int8_t	dc_nways;
 		u_int16_t	dc_nsets;
diff --git a/sys/mips/include/cpuregs.h b/sys/mips/include/cpuregs.h
index e590c9de4fe..e3070bab3b2 100644
--- a/sys/mips/include/cpuregs.h
+++ b/sys/mips/include/cpuregs.h
@@ -103,6 +103,8 @@
 /* CPU dependent mtc0 hazard hook */
 #ifdef TARGET_OCTEON
 #define	COP0_SYNC  nop; nop; nop; nop; nop;
+#elif defined(CPU_SB1)
+#define COP0_SYNC  ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop
 #else
 #define	COP0_SYNC		/* nothing */
 #endif
@@ -848,6 +850,10 @@
 #define	MIPS_4KEc_R2	0x90	/* MIPS 4KEc_R2			ISA 32  Rel 2 */
 #define	MIPS_4KEmp_R2	0x91	/* MIPS 4KEm/4KEp_R2		ISA 32  Rel 2 */
 #define	MIPS_4KSd	0x92	/* MIPS 4KSd			ISA 32  Rel 2 */
+#define	MIPS_24K	0x93	/* MIPS 24Kc/24Kf		ISA 32  Rel 2 */
+#define	MIPS_34K	0x95	/* MIPS 34K			ISA 32  R2 MT */
+#define	MIPS_24KE	0x96	/* MIPS 24KEc			ISA 32  Rel 2 */
+#define	MIPS_74K	0x97	/* MIPS 74Kc/74Kf		ISA 32  Rel 2 */
 
 /*
  * AMD (company ID 3) use the processor ID field to donote the CPU core
diff --git a/sys/mips/include/db_machdep.h b/sys/mips/include/db_machdep.h
index 989f05c61af..ea9712005f9 100644
--- a/sys/mips/include/db_machdep.h
+++ b/sys/mips/include/db_machdep.h
@@ -46,7 +46,7 @@ typedef struct trapframe db_regs_t;
 extern db_regs_t	ddb_regs;	/* register state */
 
 typedef	vm_offset_t	db_addr_t;	/* address - unsigned */
-typedef	int		db_expr_t;	/* expression - signed */
+typedef	register_t	db_expr_t;	/* expression - signed */
 
 #if BYTE_ORDER == _BIG_ENDIAN
 #define	BYTE_MSF	(1)
@@ -94,6 +94,7 @@ db_addr_t	next_instr_address(db_addr_t, boolean_t);
 int db_inst_type(int);
 void db_dump_tlb(int, int);
 db_addr_t branch_taken(int inst, db_addr_t pc);
-void stacktrace_subr(db_regs_t *, int (*)(const char *, ...));
+void stacktrace_subr(register_t pc, register_t sp, register_t ra, int (*)(const char *, ...));
+int kdbpeek(int *);
 
 #endif	/* !_MIPS_DB_MACHDEP_H_ */
diff --git a/sys/mips/include/elf.h b/sys/mips/include/elf.h
index 995862cb927..de12b5bf440 100644
--- a/sys/mips/include/elf.h
+++ b/sys/mips/include/elf.h
@@ -41,8 +41,12 @@
 /* Information taken from MIPS ABI supplemental */
 
 #ifndef __ELF_WORD_SIZE
+#if defined(__mips_n64)
+#define	__ELF_WORD_SIZE 64	/* Used by <sys/elf_generic.h> */
+#else
 #define	__ELF_WORD_SIZE 32	/* Used by <sys/elf_generic.h> */
 #endif
+#endif
 #include <sys/elf32.h>	/* Definitions common to all 32 bit architectures. */
 #include <sys/elf64.h>	/* Definitions common to all 64 bit architectures. */
 #include <sys/elf_generic.h>
diff --git a/sys/mips/include/endian.h b/sys/mips/include/endian.h
index 1d2b4fe024f..b43b1e9bf6d 100644
--- a/sys/mips/include/endian.h
+++ b/sys/mips/include/endian.h
@@ -108,12 +108,12 @@ __bswap64_var(__uint64_t _x)
 	    ((_x << 40) & ((__uint64_t)0xff << 48)) | ((_x << 56)));
 }
 
-#define	__bswap16(x)	(__uint16_t)(__is_constant(x) ? __bswap16_const(x) : \
-	__bswap16_var(x))
-#define	__bswap32(x)	(__uint32_t)(__is_constant(x) ? __bswap32_const(x) : \
-	__bswap32_var(x))
-#define	__bswap64(x)	(__uint64_t)(__is_constant(x) ? __bswap64_const(x) : \
-	__bswap64_var(x))
+#define	__bswap16(x)	(__uint16_t)(__is_constant(x) ?		\
+	__bswap16_const((__uint16_t)x) :  __bswap16_var((__uint16_t)x))
+#define	__bswap32(x)	(__uint32_t)(__is_constant(x) ?		\
+	__bswap32_const((__uint32_t)x) :  __bswap32_var((__uint32_t)x))
+#define	__bswap64(x)	(__uint64_t)(__is_constant(x) ?		\
+	__bswap64_const((__uint64_t)x) :  __bswap64_var((__uint64_t)x))
 
 #ifdef __MIPSEB__
 #define	__htonl(x)	((__uint32_t)(x))
diff --git a/sys/mips/include/float.h b/sys/mips/include/float.h
index 750feb0886f..ff7e65cf1db 100644
--- a/sys/mips/include/float.h
+++ b/sys/mips/include/float.h
@@ -42,10 +42,10 @@ extern int __flt_rounds(void);
 __END_DECLS
 
 #define	FLT_RADIX	2		/* b */
-#ifdef SOFTFLOAT
-#define	FLT_ROUNDS	-1
-#else
+#ifdef CPU_HAVEFPU
 #define	FLT_ROUNDS	__flt_rounds() /* FP addition rounds to nearest */
+#else
+#define	FLT_ROUNDS	-1
 #endif
 /*
  * XXXMIPS: MIPS32 has both float and double type, so set FLT_EVAL_METHOD
diff --git a/sys/mips/include/hwfunc.h b/sys/mips/include/hwfunc.h
index ef5088cb8d8..16b1439a81d 100644
--- a/sys/mips/include/hwfunc.h
+++ b/sys/mips/include/hwfunc.h
@@ -29,7 +29,7 @@
 #define	_MACHINE_HWFUNC_H_
 
 struct trapframe;
-
+struct timecounter;
 /*
  * Hooks downward into hardware functionality.
  */
@@ -39,4 +39,12 @@ void platform_intr(struct trapframe *);
 void platform_reset(void);
 void platform_start(__register_t, __register_t,  __register_t, __register_t);
 
+/* For clocks and ticks and such */
+void platform_initclocks(void);
+uint64_t platform_get_frequency(void);
+unsigned platform_get_timecount(struct timecounter *);
+
+/* For hardware specific CPU initialization */
+void platform_cpu_init(void);
+void platform_secondary_init(void);
 #endif /* !_MACHINE_HWFUNC_H_ */
diff --git a/sys/mips/include/intr_machdep.h b/sys/mips/include/intr_machdep.h
index d5f26d9296b..d72828eead2 100644
--- a/sys/mips/include/intr_machdep.h
+++ b/sys/mips/include/intr_machdep.h
@@ -29,15 +29,48 @@
 #ifndef	_MACHINE_INTR_MACHDEP_H_
 #define	_MACHINE_INTR_MACHDEP_H_
 
+#ifdef TARGET_XLR_XLS
+/*
+ * XLR/XLS uses its own intr_machdep.c and has
+ * a different number of interupts. This probably
+ * should be placed somewhere else.
+ */
+
+struct mips_intrhand {
+        struct  intr_event *mih_event;
+        driver_intr_t      *mih_disable;
+        volatile long       *cntp;  /* interrupt counter */
+};
+
+extern struct mips_intrhand mips_intr_handlers[];
+#define XLR_MAX_INTR 64 
+
+#else
 #define NHARD_IRQS	6
 #define NSOFT_IRQS	2
+#endif
 
 struct trapframe;
 
-void cpu_establish_hardintr(const char *, int (*)(void*), void (*)(void*), 
+void cpu_init_interrupts(void);
+void cpu_establish_hardintr(const char *, driver_filter_t *, driver_intr_t *, 
     void *, int, int, void **);
-void cpu_establish_softintr(const char *, int (*)(void*), void (*)(void*), 
+void cpu_establish_softintr(const char *, driver_filter_t *, void (*)(void*), 
     void *, int, int, void **);
 void cpu_intr(struct trapframe *);
 
+/*
+ * Opaque datatype that represents intr counter
+ */
+typedef unsigned long* mips_intrcnt_t;
+
+mips_intrcnt_t mips_intrcnt_create(const char *);
+void mips_intrcnt_setname(mips_intrcnt_t, const char *);
+
+static __inline void
+mips_intrcnt_inc(mips_intrcnt_t counter)
+{
+	if (counter)
+		atomic_add_long(counter, 1);
+}
 #endif /* !_MACHINE_INTR_MACHDEP_H_ */
diff --git a/sys/mips/include/kdb.h b/sys/mips/include/kdb.h
index 7be4ecb5ef3..cd8c6185855 100644
--- a/sys/mips/include/kdb.h
+++ b/sys/mips/include/kdb.h
@@ -47,4 +47,8 @@ kdb_cpu_trap(int vector, int _)
 {
 }
 
+static __inline void
+kdb_cpu_sync_icache(unsigned char *addr, size_t size)
+{
+}
 #endif /* _MACHINE_KDB_H_ */
diff --git a/sys/mips/include/locore.h b/sys/mips/include/locore.h
index ce60353196a..b1b9f590589 100644
--- a/sys/mips/include/locore.h
+++ b/sys/mips/include/locore.h
@@ -60,6 +60,7 @@ typedef int mips_prid_t;
 				/*	0x09	unannounced */
 				/*	0x0a	unannounced */
 #define     MIPS_PRID_CID_LEXRA		0x0b	/* Lexra */
+#define     MIPS_PRID_CID_CAVIUM	0x0d	/* Cavium */
 #define MIPS_PRID_COPTS(x)	(((x) >> 24) & 0x00ff)	/* Company Options */
 
 #ifdef _KERNEL
diff --git a/sys/mips/include/md_var.h b/sys/mips/include/md_var.h
index 3b8d0a7e82c..a523851ca5f 100644
--- a/sys/mips/include/md_var.h
+++ b/sys/mips/include/md_var.h
@@ -39,7 +39,7 @@
 /*
  * Miscellaneous machine-dependent declarations.
  */
-extern	int	Maxmem;
+extern	long	Maxmem;
 extern	char	sigcode[];
 extern	int	szsigcode, szosigcode;
 
@@ -48,10 +48,12 @@ extern vm_offset_t kstack0;
 void	MipsSaveCurFPState(struct thread *);
 void	fork_trampoline(void);
 void	cpu_swapin(struct proc *);
-u_int	MipsEmulateBranch(struct trapframe *, int, int, u_int);
+uintptr_t MipsEmulateBranch(struct trapframe *, uintptr_t, int, uintptr_t);
+void MipsSwitchFPState(struct thread *, struct trapframe *);
 u_long	kvtop(void *addr);
 int	is_physical_memory(vm_offset_t addr);
-int	is_cacheable_mem(vm_offset_t pa);
+
+#define	is_cacheable_mem(pa)	is_physical_memory((pa))
 
 #define	MIPS_DEBUG   0
 
@@ -64,9 +66,13 @@ int	is_cacheable_mem(vm_offset_t pa);
 void	mips_vector_init(void);
 void	cpu_identify(void);
 void	mips_cpu_init(void);
+void	mips_pcpu0_init(void);
 void	mips_proc0_init(void);
 
 /* Platform call-downs. */
 void	platform_identify(void);
 
+extern int busdma_swi_pending;
+void busdma_swi(void);
+
 #endif /* !_MACHINE_MD_VAR_H_ */
diff --git a/sys/mips/include/param.h b/sys/mips/include/param.h
index b8186494046..8edd48ece16 100644
--- a/sys/mips/include/param.h
+++ b/sys/mips/include/param.h
@@ -93,7 +93,7 @@
  * This does not reflect the optimal alignment, just the possibility
  * (within reasonable limits). 
  */
-#define	ALIGNED_POINTER(p, t)	((((unsigned)(p)) & (sizeof (t) - 1)) == 0)
+#define	ALIGNED_POINTER(p, t)	((((unsigned long)(p)) & (sizeof (t) - 1)) == 0)
 
 /*
  * CACHE_LINE_SIZE is the compile-time maximum cache line size for an
@@ -154,10 +154,10 @@
 /*
  * Conversion macros
  */
-#define	mips_round_page(x)	((((unsigned)(x)) + NBPG - 1) & ~(NBPG-1))
-#define	mips_trunc_page(x)	((unsigned)(x) & ~(NBPG-1))
-#define	mips_btop(x)		((unsigned)(x) >> PGSHIFT)
-#define	mips_ptob(x)		((unsigned)(x) << PGSHIFT)
+#define	mips_round_page(x)	((((unsigned long)(x)) + NBPG - 1) & ~(NBPG-1))
+#define	mips_trunc_page(x)	((unsigned long)(x) & ~(NBPG-1))
+#define	mips_btop(x)		((unsigned long)(x) >> PGSHIFT)
+#define	mips_ptob(x)		((unsigned long)(x) << PGSHIFT)
 #define	round_page		mips_round_page
 #define	trunc_page		mips_trunc_page
 #define	atop(x)			((unsigned long)(x) >> PAGE_SHIFT)
diff --git a/sys/mips/include/pcb.h b/sys/mips/include/pcb.h
index f54f2d736c2..f95ef4d8d4a 100644
--- a/sys/mips/include/pcb.h
+++ b/sys/mips/include/pcb.h
@@ -50,7 +50,7 @@
 struct pcb
 {
 	struct trapframe pcb_regs;	/* saved CPU and registers */
-	label_t pcb_context;		/* kernel context for resume */
+	__register_t pcb_context[14];	/* kernel context for resume */
 	int	pcb_onfault;		/* for copyin/copyout faults */
 	register_t pcb_tpc;
 };
@@ -71,6 +71,7 @@ struct pcb
 #define PCB_REG_RA   10
 #define PCB_REG_SR   11
 #define PCB_REG_GP   12
+#define PCB_REG_PC   13
 
 
 #ifdef _KERNEL
diff --git a/sys/mips/include/pmap.h b/sys/mips/include/pmap.h
index 4546cffd0a7..eedd4f3f801 100644
--- a/sys/mips/include/pmap.h
+++ b/sys/mips/include/pmap.h
@@ -145,7 +145,21 @@ typedef struct pv_entry {
 #define	PMAP_DIAGNOSTIC
 #endif
 
-extern vm_offset_t phys_avail[];
+/*
+ * physmem_desc[] is a superset of phys_avail[] and describes all the
+ * memory present in the system.
+ *
+ * phys_avail[] is similar but does not include the memory stolen by
+ * pmap_steal_memory().
+ *
+ * Each memory region is described by a pair of elements in the array
+ * so we can describe up to (PHYS_AVAIL_ENTRIES / 2) distinct memory
+ * regions.
+ */
+#define	PHYS_AVAIL_ENTRIES	10
+extern vm_offset_t phys_avail[PHYS_AVAIL_ENTRIES + 2];
+extern vm_offset_t physmem_desc[PHYS_AVAIL_ENTRIES + 2];
+
 extern char *ptvmmap;		/* poor name! */
 extern vm_offset_t virtual_avail;
 extern vm_offset_t virtual_end;
@@ -172,6 +186,7 @@ void *pmap_kenter_temporary(vm_paddr_t pa, int i);
 void pmap_kenter_temporary_free(vm_paddr_t pa);
 int pmap_compute_pages_to_dump(void);
 void pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte);
+void pmap_flush_pvcache(vm_page_t m);
 
 /*
  * floating virtual pages (FPAGES)
diff --git a/sys/mips/include/proc.h b/sys/mips/include/proc.h
index 6a0ce7dc077..d09620a2d11 100644
--- a/sys/mips/include/proc.h
+++ b/sys/mips/include/proc.h
@@ -54,6 +54,7 @@ struct mdthread {
 	int	md_pc_count;		/* performance counter */
 	int	md_pc_spill;		/* performance counter spill */
 	vm_offset_t	md_realstack;
+	void	*md_tls;
 };
 
 /* md_flags */
diff --git a/sys/mips/include/profile.h b/sys/mips/include/profile.h
index 9659d1fa87d..728a468dbf4 100644
--- a/sys/mips/include/profile.h
+++ b/sys/mips/include/profile.h
@@ -41,6 +41,8 @@
 
 /*XXX The cprestore instruction is a "dummy" to shut up as(1). */
 
+/*XXX This is not MIPS64 safe. */
+
 #define	MCOUNT \
 	__asm(".globl _mcount;"		\
 	".type _mcount,@function;"	\
diff --git a/sys/mips/include/psl.h b/sys/mips/include/psl.h
index 9d05d133ee2..f02a1a95fa9 100644
--- a/sys/mips/include/psl.h
+++ b/sys/mips/include/psl.h
@@ -47,8 +47,4 @@
 #define	USERMODE(ps)	(((ps) & SR_KSU_MASK) == SR_KSU_USER)
 #define	BASEPRI(ps)	(((ps) & (INT_MASK | SR_INT_ENA_PREV)) \
 			    == (INT_MASK | SR_INT_ENA_PREV))
-
-#ifdef _KERNEL
-#include <machine/intr.h>
-#endif
 #endif	/* _MACHINE_PSL_H_ */
diff --git a/sys/mips/include/pte.h b/sys/mips/include/pte.h
index aa7e839c439..db26cbb0929 100644
--- a/sys/mips/include/pte.h
+++ b/sys/mips/include/pte.h
@@ -105,7 +105,11 @@ typedef pt_entry_t *pd_entry_t;
 #define PTE_ODDPG       0x00001000 
 /*#define	PG_ATTR		0x0000003f  Not Used */
 #define	PTE_UNCACHED	0x00000010
+#ifdef CPU_SB1
+#define	PTE_CACHE	0x00000028	/* cacheable coherent */
+#else
 #define	PTE_CACHE	0x00000018
+#endif
 /*#define	PG_CACHEMODE	0x00000038 Not Used*/
 #define	PTE_ROPAGE	(PTE_V | PTE_RO | PTE_CACHE) /* Write protected */
 #define	PTE_RWPAGE	(PTE_V | PTE_M | PTE_CACHE)  /* Not wr-prot not clean */
diff --git a/sys/mips/include/regdef.h b/sys/mips/include/regdef.h
index bb9eb3d9f81..7efdd95f7ac 100644
--- a/sys/mips/include/regdef.h
+++ b/sys/mips/include/regdef.h
@@ -12,6 +12,8 @@
 #ifndef _MACHINE_REGDEF_H_
 #define	_MACHINE_REGDEF_H_
 
+#include <machine/cdefs.h>		/* For API selection */
+
 #if defined(__ASSEMBLER__)
 /* General purpose CPU register names */
 #define	zero	$0	/* wired zero */
@@ -22,6 +24,16 @@
 #define	a1	$5
 #define	a2	$6
 #define	a3	$7
+#if defined(__mips_n32) || defined(__mips_n64)
+#define	a4	$8
+#define	a5	$9
+#define	a6	$10
+#define	a7	$11
+#define	t0	$12	/* Temp regs, not saved accross subroutine calls */
+#define	t1	$13
+#define	t2	$14
+#define	t3	$15
+#else
 #define	t0	$8	/* caller saved */
 #define	t1	$9
 #define	t2	$10
@@ -30,6 +42,7 @@
 #define	t5	$13
 #define	t6	$14
 #define	t7	$15
+#endif
 #define	s0	$16	/* callee saved */
 #define	s1	$17
 #define	s2	$18
@@ -48,6 +61,26 @@
 #define	s8	$30	/* callee saved */
 #define	ra	$31	/* return address */
 
+/*
+ * These are temp registers whose names can be used in either the old
+ * or new ABI, although they map to different physical registers.  In
+ * the old ABI, they map to t4-t7, and in the new ABI, they map to a4-a7.
+ *
+ * Because they overlap with the last 4 arg regs in the new ABI, ta0-ta3
+ * should be used only when we need more than t0-t3.
+ */
+#if defined(__mips_n32) || defined(__mips_n64)
+#define	ta0	$8
+#define	ta1	$9
+#define	ta2	$10
+#define	ta3	$11
+#else
+#define	ta0	$12
+#define	ta1	$13
+#define	ta2	$14
+#define	ta3	$15
+#endif /* __mips_n32 || __mips_n64 */
+
 #endif /* __ASSEMBLER__ */
 
 #endif /* !_MACHINE_REGDEF_H_ */
diff --git a/sys/mips/include/regnum.h b/sys/mips/include/regnum.h
index 1e3f2c875b9..baa60bd8b86 100644
--- a/sys/mips/include/regnum.h
+++ b/sys/mips/include/regnum.h
@@ -63,8 +63,7 @@
 #define PREG_RA   10
 #define PREG_SR   11
 #define PREG_GP   12
-
-
+#define PREG_PC   13
 
 /*
  * Location of the saved registers relative to ZERO.
@@ -82,10 +81,10 @@
 #define	T1	9
 #define	T2	10
 #define	T3	11
-#define	T4	12
-#define	T5	13
-#define	T6	14
-#define	T7	15
+#define	TA0	12
+#define	TA1	13
+#define	TA2	14
+#define	TA3	15
 #define	S0	16
 #define	S1	17
 #define	S2	18
diff --git a/sys/mips/include/trap.h b/sys/mips/include/trap.h
index a00ca908f2f..3d0470eb3ce 100644
--- a/sys/mips/include/trap.h
+++ b/sys/mips/include/trap.h
@@ -108,6 +108,18 @@ void trapDump(char *msg);
 
 #endif
 
+void MipsFPTrap(u_int, u_int, u_int);
+void MipsKernGenException(void);
+void MipsKernIntr(void);
+void MipsKernTLBInvalidException(void);
+void MipsTLBInvalidException(void);
+void MipsTLBMissException(void);
+void MipsUserGenException(void);
+void MipsUserIntr(void);
+void MipsUserTLBInvalidException(void);
+
+u_int trap(struct trapframe *);
+
 #ifndef LOCORE /* XXX */
 int check_address(void *);
 void platform_trap_enter(void);
diff --git a/sys/mips/include/ucontext.h b/sys/mips/include/ucontext.h
index d9dfe4ea09f..c360a65b870 100644
--- a/sys/mips/include/ucontext.h
+++ b/sys/mips/include/ucontext.h
@@ -53,14 +53,19 @@ typedef struct	__mcontext {
 	int		mc_fpused;	/* fp has been used */
 	f_register_t	mc_fpregs[33];	/* fp regs 0 to 31 and csr */
 	register_t	mc_fpc_eir;	/* fp exception instruction reg */
+	void		*mc_tls;	/* pointer to TLS area */
 	int	__spare__[8];	/* XXX reserved */ 
 } mcontext_t;
 #endif
 
+#if defined(__mips_n64) || defined(__mips_n32)
+#define	SZREG		8
+#else
 #define	SZREG		4
+#endif
 
 /* offsets into mcontext_t */
-#define	UCTX_REG(x)	(8 + (x)*SZREG)
+#define	UCTX_REG(x)	(4 + SZREG + (x)*SZREG)
 
 #define	UCR_ZERO	UCTX_REG(0)
 #define	UCR_AT		UCTX_REG(1)