From 2b2c134337ff45b9ab3c409a5343f4fb04c4f4de Mon Sep 17 00:00:00 2001 From: Zachary Leaf Date: Wed, 20 Sep 2023 10:51:22 +0100 Subject: [PATCH] arm64: add PMBSR_MSS_{BSC,FSC} status code field Bits [5:0] of PMBSR_MSS encodes either Buffer Status Code (BSC) or Fault Status Code (FSC) depending on PMBSR_EC value. Add PMBSR_MSS_{BSC,FSC} to cover this field. Reviewed by: andrew Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D45172 (cherry picked from commit 10b3eac88db689d657c4d0d0716bcbdf240ff614) --- sys/arm64/include/armreg.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index ca281e80043..e90c6a57fd5 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -1689,6 +1689,8 @@ #define PMBSR_EL1_op2 3 #define PMBSR_MSS_SHIFT 0 #define PMBSR_MSS_MASK (UL(0xffff) << PMBSR_MSS_SHIFT) +#define PMBSR_MSS_BSC_MASK (UL(0x3f) << PMBSR_MSS_SHIFT) +#define PMBSR_MSS_FSC_MASK (UL(0x3f) << PMBSR_MSS_SHIFT) #define PMBSR_COLL_SHIFT 16 #define PMBSR_COLL (UL(0x1) << PMBSR_COLL_SHIFT) #define PMBSR_S_SHIFT 17