From 2ac5ef02d43bf2b517cae04eebbcff57bffe62b3 Mon Sep 17 00:00:00 2001 From: Kyle Evans Date: Thu, 14 Jun 2018 18:34:02 +0000 Subject: [PATCH] a10_ahci: Correct clock indices for new bindings r329104 imported 4.15 DTS which brought CCU to a10/a20. In the process, they swapped the ordering of 'clocks' for allwinner,sun4i-a10-ahci on both sun4i-a10 and sun7i-a20 from PLL, Gate to Gate, PLL. Swap it in the driver. --- sys/arm/allwinner/a10_ahci.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/sys/arm/allwinner/a10_ahci.c b/sys/arm/allwinner/a10_ahci.c index 69efe507172..7e149e2dd9e 100644 --- a/sys/arm/allwinner/a10_ahci.c +++ b/sys/arm/allwinner/a10_ahci.c @@ -313,16 +313,16 @@ ahci_a10_attach(device_t dev) return (ENXIO); /* Enable clocks */ - error = clk_get_by_ofw_index(dev, 0, 0, &clk_pll); - if (error != 0) { - device_printf(dev, "Cannot get PLL clock\n"); - goto fail; - } - error = clk_get_by_ofw_index(dev, 0, 1, &clk_gate); + error = clk_get_by_ofw_index(dev, 0, 0, &clk_gate); if (error != 0) { device_printf(dev, "Cannot get gate clock\n"); goto fail; } + error = clk_get_by_ofw_index(dev, 0, 1, &clk_pll); + if (error != 0) { + device_printf(dev, "Cannot get PLL clock\n"); + goto fail; + } error = clk_set_freq(clk_pll, PLL_FREQ, CLK_SET_ROUND_DOWN); if (error != 0) { device_printf(dev, "Cannot set PLL frequency\n");