From 29f0d43398d2c857c1754b3a3a454014a9fcfe37 Mon Sep 17 00:00:00 2001 From: Warner Losh Date: Mon, 16 Oct 2000 19:49:30 +0000 Subject: [PATCH] Add types and prototypes. Submitted by: msmith --- sys/amd64/include/pc/bios.h | 46 +++++++++++++++++++++++++++++++++- sys/amd64/include/pci_cfgreg.h | 2 +- sys/i386/include/pc/bios.h | 46 +++++++++++++++++++++++++++++++++- sys/i386/include/pci_cfgreg.h | 2 +- 4 files changed, 92 insertions(+), 4 deletions(-) diff --git a/sys/amd64/include/pc/bios.h b/sys/amd64/include/pc/bios.h index 9df5a0dcaae..7a838b8cb05 100644 --- a/sys/amd64/include/pc/bios.h +++ b/sys/amd64/include/pc/bios.h @@ -219,6 +219,51 @@ extern int bios16_call(struct bios_regs *, char *); extern int bios32(struct bios_regs *, u_int, u_short); extern void set_bios_selectors(struct bios_segments *, int); +/* + * PCI interrupt routing table. + * + * $PIR in the BIOS segment contains a PIR_table + * int 1a:b106 returns PIR_table in buffer at es:(e)di + * int 1a:b18e returns PIR_table in buffer at es:(e)di + * int 1a:b406 returns es:di pointing to the BIOS PIR_table + */ +struct PIR_header +{ + int8_t ph_signature[4]; + u_int16_t ph_version; + u_int16_t ph_length; + u_int8_t ph_router_bus; + u_int8_t ph_router_dev_fn; + u_int16_t ph_pci_irqs; + u_int16_t ph_router_vendor; + u_int16_t ph_router_device; + u_int32_t ph_miniport; + u_int8_t ph_res[11]; + u_int8_t ph_checksum; +} __attribute__ ((packed)); + +struct PIR_intpin +{ + u_int8_t link; + u_int16_t irqs; +} __attribute__ ((packed)); + +struct PIR_entry +{ + u_int8_t pe_bus; + u_int8_t pe_res1:3; + u_int8_t pe_device:5; + struct PIR_intpin pe_intpin[4]; + u_int8_t pe_slot; + u_int8_t pe_res3; +} __attribute__ ((packed)); + +struct PIR_table +{ + struct PIR_header pt_header; + struct PIR_entry pt_entry[0]; +} __attribute__ ((packed)); + /* * Int 15:E820 'SMAP' structure * @@ -230,4 +275,3 @@ struct bios_smap { u_int64_t length; u_int32_t type; } __attribute__ ((packed)); - diff --git a/sys/amd64/include/pci_cfgreg.h b/sys/amd64/include/pci_cfgreg.h index c0909aaf170..6e79a22fc6d 100644 --- a/sys/amd64/include/pci_cfgreg.h +++ b/sys/amd64/include/pci_cfgreg.h @@ -50,4 +50,4 @@ extern int pci_cfgregopen(void); extern u_int32_t pci_cfgregread(int bus, int slot, int func, int reg, int bytes); extern void pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes); - +extern int pci_cfgintr(int bus, int device, int pin); diff --git a/sys/i386/include/pc/bios.h b/sys/i386/include/pc/bios.h index 9df5a0dcaae..7a838b8cb05 100644 --- a/sys/i386/include/pc/bios.h +++ b/sys/i386/include/pc/bios.h @@ -219,6 +219,51 @@ extern int bios16_call(struct bios_regs *, char *); extern int bios32(struct bios_regs *, u_int, u_short); extern void set_bios_selectors(struct bios_segments *, int); +/* + * PCI interrupt routing table. + * + * $PIR in the BIOS segment contains a PIR_table + * int 1a:b106 returns PIR_table in buffer at es:(e)di + * int 1a:b18e returns PIR_table in buffer at es:(e)di + * int 1a:b406 returns es:di pointing to the BIOS PIR_table + */ +struct PIR_header +{ + int8_t ph_signature[4]; + u_int16_t ph_version; + u_int16_t ph_length; + u_int8_t ph_router_bus; + u_int8_t ph_router_dev_fn; + u_int16_t ph_pci_irqs; + u_int16_t ph_router_vendor; + u_int16_t ph_router_device; + u_int32_t ph_miniport; + u_int8_t ph_res[11]; + u_int8_t ph_checksum; +} __attribute__ ((packed)); + +struct PIR_intpin +{ + u_int8_t link; + u_int16_t irqs; +} __attribute__ ((packed)); + +struct PIR_entry +{ + u_int8_t pe_bus; + u_int8_t pe_res1:3; + u_int8_t pe_device:5; + struct PIR_intpin pe_intpin[4]; + u_int8_t pe_slot; + u_int8_t pe_res3; +} __attribute__ ((packed)); + +struct PIR_table +{ + struct PIR_header pt_header; + struct PIR_entry pt_entry[0]; +} __attribute__ ((packed)); + /* * Int 15:E820 'SMAP' structure * @@ -230,4 +275,3 @@ struct bios_smap { u_int64_t length; u_int32_t type; } __attribute__ ((packed)); - diff --git a/sys/i386/include/pci_cfgreg.h b/sys/i386/include/pci_cfgreg.h index c0909aaf170..6e79a22fc6d 100644 --- a/sys/i386/include/pci_cfgreg.h +++ b/sys/i386/include/pci_cfgreg.h @@ -50,4 +50,4 @@ extern int pci_cfgregopen(void); extern u_int32_t pci_cfgregread(int bus, int slot, int func, int reg, int bytes); extern void pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes); - +extern int pci_cfgintr(int bus, int device, int pin);