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amd64: add machine/pte.h
Following arm64 and risc-v, move definitions that describe hardware-enforced layout of PTEs and #PF error bits, into a dedicated header. Reviewed by: markj Sponsored by: The FreeBSD Foundation MFC after: 1 week Differential revision: https://reviews.freebsd.org/D47749
This commit is contained in:
Konstantin Belousov
parent
10ffe0f957
commit
28fdf718b3
2 changed files with 105 additions and 57 deletions
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@ -47,48 +47,7 @@
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#ifndef _MACHINE_PMAP_H_
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#define _MACHINE_PMAP_H_
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/*
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* Page-directory and page-table entries follow this format, with a few
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* of the fields not present here and there, depending on a lot of things.
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*/
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/* ---- Intel Nomenclature ---- */
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#define X86_PG_V 0x001 /* P Valid */
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#define X86_PG_RW 0x002 /* R/W Read/Write */
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#define X86_PG_U 0x004 /* U/S User/Supervisor */
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#define X86_PG_NC_PWT 0x008 /* PWT Write through */
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#define X86_PG_NC_PCD 0x010 /* PCD Cache disable */
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#define X86_PG_A 0x020 /* A Accessed */
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#define X86_PG_M 0x040 /* D Dirty */
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#define X86_PG_PS 0x080 /* PS Page size (0=4k,1=2M) */
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#define X86_PG_PTE_PAT 0x080 /* PAT PAT index */
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#define X86_PG_G 0x100 /* G Global */
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#define X86_PG_AVAIL1 0x200 /* / Available for system */
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#define X86_PG_AVAIL2 0x400 /* < programmers use */
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#define X86_PG_AVAIL3 0x800 /* \ */
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#define X86_PG_PDE_PAT 0x1000 /* PAT PAT index */
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#define X86_PG_PKU(idx) ((pt_entry_t)idx << 59)
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#define X86_PG_NX (1ul<<63) /* No-execute */
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#define X86_PG_AVAIL(x) (1ul << (x))
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/* Page level cache control fields used to determine the PAT type */
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#define X86_PG_PDE_CACHE (X86_PG_PDE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD)
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#define X86_PG_PTE_CACHE (X86_PG_PTE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD)
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/* Protection keys indexes */
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#define PMAP_MAX_PKRU_IDX 0xf
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#define X86_PG_PKU_MASK X86_PG_PKU(PMAP_MAX_PKRU_IDX)
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/*
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* Intel extended page table (EPT) bit definitions.
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*/
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#define EPT_PG_READ 0x001 /* R Read */
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#define EPT_PG_WRITE 0x002 /* W Write */
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#define EPT_PG_EXECUTE 0x004 /* X Execute */
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#define EPT_PG_IGNORE_PAT 0x040 /* IPAT Ignore PAT */
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#define EPT_PG_PS 0x080 /* PS Page size */
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#define EPT_PG_A 0x100 /* A Accessed */
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#define EPT_PG_M 0x200 /* D Dirty */
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#define EPT_PG_MEMORY_TYPE(x) ((x) << 3) /* MT Memory Type */
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#include <machine/pte.h>
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/*
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* Define the PG_xx macros in terms of the bits on x86 PTEs.
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@ -117,9 +76,6 @@
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#define EPT_PG_EMUL_V X86_PG_AVAIL(52)
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#define EPT_PG_EMUL_RW X86_PG_AVAIL(53)
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#define PG_PROMOTED X86_PG_AVAIL(54) /* PDE only */
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#define PG_FRAME (0x000ffffffffff000ul)
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#define PG_PS_FRAME (0x000fffffffe00000ul)
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#define PG_PS_PDP_FRAME (0x000fffffc0000000ul)
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/*
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* Promotion to a 2MB (PDE) page mapping requires that the corresponding 4KB
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@ -128,18 +84,6 @@
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#define PG_PTE_PROMOTE (PG_NX | PG_MANAGED | PG_W | PG_G | PG_PTE_CACHE | \
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PG_M | PG_U | PG_RW | PG_V | PG_PKU_MASK)
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/*
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* Page Protection Exception bits
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*/
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#define PGEX_P 0x01 /* Protection violation vs. not present */
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#define PGEX_W 0x02 /* during a Write cycle */
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#define PGEX_U 0x04 /* access from User mode (UPL) */
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#define PGEX_RSV 0x08 /* reserved PTE field is non-zero */
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#define PGEX_I 0x10 /* during an instruction fetch */
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#define PGEX_PK 0x20 /* protection key violation */
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#define PGEX_SGX 0x8000 /* SGX-related */
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/*
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* undef the PG_xx macros that define bits in the regular x86 PTEs that
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* have a different position in nested PTEs. This is done when compiling
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104
sys/amd64/include/pte.h
Normal file
104
sys/amd64/include/pte.h
Normal file
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@ -0,0 +1,104 @@
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/*-
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 2003 Peter Wemm.
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* Copyright (c) 1991 Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department and William Jolitz of UUNET Technologies Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Derived from hp300 version by Mike Hibler, this version by William
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* Jolitz uses a recursive map [a pde points to the page directory] to
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* map the page tables using the pagetables themselves. This is done to
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* reduce the impact on kernel virtual memory for lots of sparse address
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* space, and to reduce the cost of memory to each process.
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*/
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#ifndef _MACHINE_PTE_H_
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#define _MACHINE_PTE_H_
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/*
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* Page-directory and page-table entries follow this format, with a few
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* of the fields not present here and there, depending on a lot of things.
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*/
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/* ---- Intel Nomenclature ---- */
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#define X86_PG_V 0x001 /* P Valid */
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#define X86_PG_RW 0x002 /* R/W Read/Write */
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#define X86_PG_U 0x004 /* U/S User/Supervisor */
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#define X86_PG_NC_PWT 0x008 /* PWT Write through */
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#define X86_PG_NC_PCD 0x010 /* PCD Cache disable */
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#define X86_PG_A 0x020 /* A Accessed */
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#define X86_PG_M 0x040 /* D Dirty */
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#define X86_PG_PS 0x080 /* PS Page size (0=4k,1=2M) */
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#define X86_PG_PTE_PAT 0x080 /* PAT PAT index */
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#define X86_PG_G 0x100 /* G Global */
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#define X86_PG_AVAIL1 0x200 /* / Available for system */
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#define X86_PG_AVAIL2 0x400 /* < programmers use */
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#define X86_PG_AVAIL3 0x800 /* \ */
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#define X86_PG_PDE_PAT 0x1000 /* PAT PAT index */
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#define X86_PG_PKU(idx) ((pt_entry_t)idx << 59)
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#define X86_PG_NX (1ul<<63) /* No-execute */
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#define X86_PG_AVAIL(x) (1ul << (x))
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/* Page level cache control fields used to determine the PAT type */
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#define X86_PG_PDE_CACHE (X86_PG_PDE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD)
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#define X86_PG_PTE_CACHE (X86_PG_PTE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD)
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/* Protection keys indexes */
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#define PMAP_MAX_PKRU_IDX 0xf
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#define X86_PG_PKU_MASK X86_PG_PKU(PMAP_MAX_PKRU_IDX)
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/*
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* Intel extended page table (EPT) bit definitions.
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*/
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#define EPT_PG_READ 0x001 /* R Read */
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#define EPT_PG_WRITE 0x002 /* W Write */
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#define EPT_PG_EXECUTE 0x004 /* X Execute */
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#define EPT_PG_IGNORE_PAT 0x040 /* IPAT Ignore PAT */
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#define EPT_PG_PS 0x080 /* PS Page size */
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#define EPT_PG_A 0x100 /* A Accessed */
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#define EPT_PG_M 0x200 /* D Dirty */
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#define EPT_PG_MEMORY_TYPE(x) ((x) << 3) /* MT Memory Type */
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#define PG_FRAME (0x000ffffffffff000ul)
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#define PG_PS_FRAME (0x000fffffffe00000ul)
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#define PG_PS_PDP_FRAME (0x000fffffc0000000ul)
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/*
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* Page Protection Exception bits
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*/
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#define PGEX_P 0x01 /* Protection violation vs. not present */
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#define PGEX_W 0x02 /* during a Write cycle */
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#define PGEX_U 0x04 /* access from User mode (UPL) */
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#define PGEX_RSV 0x08 /* reserved PTE field is non-zero */
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#define PGEX_I 0x10 /* during an instruction fetch */
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#define PGEX_PK 0x20 /* protection key violation */
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#define PGEX_SGX 0x8000 /* SGX-related */
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#endif
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