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Add driver for DM&P Vortex86 RDC R6040 Fast Ethernet.
The controller is commonly found on DM&P Vortex86 x86 SoC. The driver supports all hardware features except flow control. The flow control was intentionally disabled due to silicon bug. DM&P Electronics, Inc. provided all necessary information including sample board to write driver and answered many questions I had. Many thanks for their support of FreeBSD. H/W donated by: DM&P Electronics, Inc.
This commit is contained in:
Pyun YongHyeon
parent
e6713fe53c
commit
2608aefc0b
9 changed files with 2585 additions and 0 deletions
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@ -328,6 +328,7 @@ if_tl_load="NO" # Texas Instruments TNETE100 ("ThunderLAN")
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if_tx_load="NO" # SMC 83c17x Fast Ethernet
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if_txp_load="NO" # 3Com 3XP Typhoon/Sidewinder (3CR990)
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if_vge_load="NO" # VIA VT6122 PCI Gigabit Ethernet
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if_vte_load="NO" # DM&P Vortex86 RDC R6040 Fast Ethernet
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if_uath_load="NO" # Atheros USB wireless for AR5005UG & AR5005UX
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if_udav_load="NO" # Davicom DM9601 USB Ethernet
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if_upgt_load="NO" # Conexant/Intersil PrismGT USB wireless
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@ -1995,6 +1995,7 @@ device xmphy # XaQti XMAC II
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# Technologies VT3043 `Rhine I' and VT86C100A `Rhine II' chips,
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# including the D-Link DFE520TX and D-Link DFE530TX (see 'rl' for
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# DFE530TX+), the Hawking Technologies PN102TX, and the AOpen/Acer ALN-320.
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# vte: DM&P Vortex86 RDC R6040 Fast Ethernet
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# vx: 3Com 3C590 and 3C595
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# wb: Support for fast ethernet adapters based on the Winbond W89C840F chip.
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# Note: this is not the same as the Winbond W89C940F, which is a
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@ -2067,6 +2068,7 @@ device stge # Sundance/Tamarack TC9021 gigabit Ethernet
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device tl # Texas Instruments ThunderLAN
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device tx # SMC EtherPower II (83c170 ``EPIC'')
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device vr # VIA Rhine, Rhine II
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device vte # DM&P Vortex86 RDC R6040 Fast Ethernet
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device wb # Winbond W89C840F
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device xl # 3Com 3c90x (``Boomerang'', ``Cyclone'')
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@ -1876,6 +1876,7 @@ dev/utopia/utopia.c optional utopia
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dev/vge/if_vge.c optional vge
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dev/vkbd/vkbd.c optional vkbd
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dev/vr/if_vr.c optional vr pci
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dev/vte/if_vte.c optional vte pci
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dev/vx/if_vx.c optional vx
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dev/vx/if_vx_eisa.c optional vx eisa
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dev/vx/if_vx_pci.c optional vx pci
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2056
sys/dev/vte/if_vte.c
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2056
sys/dev/vte/if_vte.c
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File diff suppressed because it is too large
Load diff
346
sys/dev/vte/if_vtereg.h
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346
sys/dev/vte/if_vtereg.h
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@ -0,0 +1,346 @@
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/*-
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* Copyright (c) 2010, Pyun YongHyeon <yongari@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _IF_VTEREG_H
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#define _IF_VTEREG_H
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/*
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* RDC Semiconductor PCI vendor ID
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*/
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#define VENDORID_RDC 0x17F3
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/*
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* Vortex86 RDC R6040 FastEthernet device ID
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*/
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#define DEVICEID_RDC_R6040 0x6040 /* PMX-1000 */
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/* MAC control register 0 */
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#define VTE_MCR0 0x00
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#define MCR0_ACCPT_ERR 0x0001
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#define MCR0_RX_ENB 0x0002
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#define MCR0_ACCPT_RUNT 0x0004
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#define MCR0_ACCPT_LONG_PKT 0x0008
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#define MCR0_ACCPT_DRIBBLE 0x0010
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#define MCR0_PROMISC 0x0020
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#define MCR0_BROADCAST 0x0040
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#define MCR0_RX_EARLY_INTR 0x0080
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#define MCR0_MULTICAST 0x0100
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#define MCR0_FC_ENB 0x0200
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#define MCR0_TX_ENB 0x1000
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#define MCR0_TX_EARLY_INTR 0x4000
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#define MCR0_FULL_DUPLEX 0x8000
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/* MAC control register 1 */
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#define VTE_MCR1 0x04
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#define MCR1_MAC_RESET 0x0001
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#define MCR1_MAC_LOOPBACK 0x0002
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#define MCR1_EXCESS_COL_RETRANS_DIS 0x0004
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#define MCR1_AUTO_CHG_DUPLEX 0x0008
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#define MCR1_PKT_LENGTH_1518 0x0010
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#define MCR1_PKT_LENGTH_1522 0x0020
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#define MCR1_PKT_LENGTH_1534 0x0030
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#define MCR1_PKT_LENGTH_1537 0x0000
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#define MCR1_EARLY_INTR_THRESH_1129 0x0000
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#define MCR1_EARLY_INTR_THRESH_1257 0x0040
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#define MCR1_EARLY_INTR_THRESH_1385 0x0080
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#define MCR1_EARLY_INTR_THRESH_1513 0x00C0
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#define MCR1_EXCESS_COL_RETRY_16 0x0000
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#define MCR1_EXCESS_COL_RETRY_32 0x0100
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#define MCR1_FC_ACTIVE 0x0200
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#define MCR1_RX_DESC_HASH_IDX 0x4000
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#define MCR1_RX_UNICAST_HASH 0x8000
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#define MCR1_PKT_LENGTH_MASK 0x0030
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#define MCR1_EARLY_INTR_THRESH_MASK 0x00C0
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/* MAC bus control register */
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#define VTE_MBCR 0x08
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#define MBCR_FIFO_XFER_LENGTH_4 0x0000
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#define MBCR_FIFO_XFER_LENGTH_8 0x0001
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#define MBCR_FIFO_XFER_LENGTH_16 0x0002
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#define MBCR_FIFO_XFER_LENGTH_32 0x0003
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#define MBCR_TX_FIFO_THRESH_16 0x0000
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#define MBCR_TX_FIFO_THRESH_32 0x0004
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#define MBCR_TX_FIFO_THRESH_64 0x0008
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#define MBCR_TX_FIFO_THRESH_96 0x000C
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#define MBCR_RX_FIFO_THRESH_8 0x0000
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#define MBCR_RX_FIFO_THRESH_16 0x0010
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#define MBCR_RX_FIFO_THRESH_32 0x0020
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#define MBCR_RX_FIFO_THRESH_64 0x0030
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#define MBCR_SDRAM_BUS_REQ_TIMER_MASK 0x1F00
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#define MBCR_SDRAM_BUS_REQ_TIMER_SHIFT 8
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#define MBCR_SDRAM_BUS_REQ_TIMER_DEFAULT 0x1F00
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/* MAC TX interrupt control register */
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#define VTE_MTICR 0x0C
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#define MTICR_TX_TIMER_MASK 0x001F
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#define MTICR_TX_BUNDLE_MASK 0x0F00
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#define VTE_IM_TX_TIMER_DEFAULT 0x7F
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#define VTE_IM_TX_BUNDLE_DEFAULT 15
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#define VTE_IM_TIMER_MIN 0
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#define VTE_IM_TIMER_MAX 82
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#define VTE_IM_TIMER_MASK 0x001F
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#define VTE_IM_TIMER_SHIFT 0
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#define VTE_IM_BUNDLE_MIN 1
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#define VTE_IM_BUNDLE_MAX 15
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#define VTE_IM_BUNDLE_SHIFT 8
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/* MAC RX interrupt control register */
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#define VTE_MRICR 0x10
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#define MRICR_RX_TIMER_MASK 0x001F
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#define MRICR_RX_BUNDLE_MASK 0x0F00
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#define VTE_IM_RX_TIMER_DEFAULT 0x7F
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#define VTE_IM_RX_BUNDLE_DEFAULT 15
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/* MAC TX poll command register */
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#define VTE_TX_POLL 0x14
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#define TX_POLL_START 0x0001
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/* MAC RX buffer size register */
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#define VTE_MRBSR 0x18
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#define VTE_MRBSR_SIZE_MASK 0x03FF
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/* MAC RX descriptor control register */
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#define VTE_MRDCR 0x1A
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#define VTE_MRDCR_RESIDUE_MASK 0x00FF
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#define VTE_MRDCR_RX_PAUSE_THRESH_MASK 0xFF00
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#define VTE_MRDCR_RX_PAUSE_THRESH_SHIFT 8
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/* MAC Last status register */
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#define VTE_MLSR 0x1C
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#define MLSR_MULTICAST 0x0001
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#define MLSR_BROADCAST 0x0002
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#define MLSR_CRC_ERR 0x0004
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#define MLSR_RUNT 0x0008
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#define MLSR_LONG_PKT 0x0010
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#define MLSR_TRUNC 0x0020
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#define MLSR_DRIBBLE 0x0040
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#define MLSR_PHY_ERR 0x0080
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#define MLSR_TX_FIFO_UNDERRUN 0x0200
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#define MLSR_RX_DESC_UNAVAIL 0x0400
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#define MLSR_TX_EXCESS_COL 0x2000
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#define MLSR_TX_LATE_COL 0x4000
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#define MLSR_RX_FIFO_OVERRUN 0x8000
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/* MAC MDIO control register */
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#define VTE_MMDIO 0x20
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#define MMDIO_REG_ADDR_MASK 0x001F
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#define MMDIO_PHY_ADDR_MASK 0x1F00
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#define MMDIO_READ 0x2000
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#define MMDIO_WRITE 0x4000
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#define MMDIO_REG_ADDR_SHIFT 0
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#define MMDIO_PHY_ADDR_SHIFT 8
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/* MAC MDIO read data register */
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#define VTE_MMRD 0x24
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#define MMRD_DATA_MASK 0xFFFF
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/* MAC MDIO write data register */
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#define VTE_MMWD 0x28
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#define MMWD_DATA_MASK 0xFFFF
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/* MAC TX descriptor start address 0 */
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#define VTE_MTDSA0 0x2C
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/* MAC TX descriptor start address 1 */
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#define VTE_MTDSA1 0x30
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/* MAC RX descriptor start address 0 */
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#define VTE_MRDSA0 0x34
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/* MAC RX descriptor start address 1 */
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#define VTE_MRDSA1 0x38
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/* MAC Interrupt status register */
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#define VTE_MISR 0x3C
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#define MISR_RX_DONE 0x0001
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#define MISR_RX_DESC_UNAVAIL 0x0002
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#define MISR_RX_FIFO_FULL 0x0004
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#define MISR_RX_EARLY_INTR 0x0008
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#define MISR_TX_DONE 0x0010
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#define MISR_TX_EARLY_INTR 0x0080
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#define MISR_EVENT_CNT_OFLOW 0x0100
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#define MISR_PHY_MEDIA_CHG 0x0200
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/* MAC Interrupt enable register */
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#define VTE_MIER 0x40
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#define VTE_INTRS \
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(MISR_RX_DONE | MISR_RX_DESC_UNAVAIL | MISR_RX_FIFO_FULL | \
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MISR_TX_DONE | MISR_EVENT_CNT_OFLOW)
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/* MAC Event counter interrupt status register */
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#define VTE_MECISR 0x44
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#define MECISR_EC_RX_DONE 0x0001
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#define MECISR_EC_MULTICAST 0x0002
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#define MECISR_EC_BROADCAST 0x0004
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#define MECISR_EC_CRC_ERR 0x0008
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#define MECISR_EC_RUNT 0x0010
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#define MESCIR_EC_LONG_PKT 0x0020
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#define MESCIR_EC_RX_DESC_UNAVAIL 0x0080
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#define MESCIR_EC_RX_FIFO_FULL 0x0100
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#define MESCIR_EC_TX_DONE 0x0200
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#define MESCIR_EC_LATE_COL 0x0400
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#define MESCIR_EC_TX_UNDERRUN 0x0800
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/* MAC Event counter interrupt enable register */
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#define VTE_MECIER 0x48
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#define VTE_MECIER_INTRS \
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(MECISR_EC_RX_DONE | MECISR_EC_MULTICAST | MECISR_EC_BROADCAST | \
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MECISR_EC_CRC_ERR | MECISR_EC_RUNT | MESCIR_EC_LONG_PKT | \
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MESCIR_EC_RX_DESC_UNAVAIL | MESCIR_EC_RX_FIFO_FULL | \
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MESCIR_EC_TX_DONE | MESCIR_EC_LATE_COL | MESCIR_EC_TX_UNDERRUN)
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#define VTE_CNT_RX_DONE 0x50
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#define VTE_CNT_MECNT0 0x52
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#define VTE_CNT_MECNT1 0x54
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#define VTE_CNT_MECNT2 0x56
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#define VTE_CNT_MECNT3 0x58
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#define VTE_CNT_TX_DONE 0x5A
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#define VTE_CNT_MECNT4 0x5C
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#define VTE_CNT_PAUSE 0x5E
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/* MAC Hash table register */
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#define VTE_MAR0 0x60
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#define VTE_MAR1 0x62
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#define VTE_MAR2 0x64
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#define VTE_MAR3 0x66
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/* MAC station address and multicast address register */
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#define VTE_MID0L 0x68
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#define VTE_MID0M 0x6A
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#define VTE_MID0H 0x6C
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#define VTE_MID1L 0x70
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#define VTE_MID1M 0x72
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#define VTE_MID1H 0x74
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#define VTE_MID2L 0x78
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#define VTE_MID2M 0x7A
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#define VTE_MID2H 0x7C
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#define VTE_MID3L 0x80
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#define VTE_MID3M 0x82
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#define VTE_MID3H 0x84
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#define VTE_RXFILTER_PEEFECT_BASE VTE_MID1L
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#define VTE_RXFILT_PERFECT_CNT 3
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/* MAC PHY status change configuration register */
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#define VTE_MPSCCR 0x88
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#define MPSCCR_TIMER_DIVIDER_MASK 0x0007
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#define MPSCCR_PHY_ADDR_MASK 0x1F00
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#define MPSCCR_PHY_STS_CHG_ENB 0x8000
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#define MPSCCR_PHY_ADDR_SHIFT 8
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/* MAC PHY status register2 */
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#define VTE_MPSR 0x8A
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#define MPSR_LINK_UP 0x0001
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#define MPSR_SPEED_100 0x0002
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#define MPSR_FULL_DUPLEX 0x0004
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/* MAC Status machine(undocumented). */
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#define VTE_MACSM 0xAC
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/* MDC Speed control register */
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#define VTE_MDCSC 0xB6
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#define MDCSC_DEFAULT 0x0030
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/* MAC Identifier and revision register */
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#define VTE_MACID_REV 0xBC
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#define VTE_MACID_REV_MASK 0x00FF
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#define VTE_MACID_MASK 0xFF00
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#define VTE_MACID_REV_SHIFT 0
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#define VTE_MACID_SHIFT 8
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/* MAC Identifier register */
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#define VTE_MACID 0xBE
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/*
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* RX descriptor
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* - Added one more uint16_t member to align it 4 on bytes boundary.
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* This does not affect operation of controller since it includes
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* next pointer address.
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*/
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struct vte_rx_desc {
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uint16_t drst;
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uint16_t drlen;
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uint32_t drbp;
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uint32_t drnp;
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uint16_t hidx;
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uint16_t rsvd2;
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uint16_t rsvd3;
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uint16_t __pad; /* Not actual descriptor member. */
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};
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#define VTE_DRST_MID_MASK 0x0003
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#define VTE_DRST_MID_HIT 0x0004
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#define VTE_DRST_MULTICAST_HIT 0x0008
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#define VTE_DRST_MULTICAST 0x0010
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#define VTE_DRST_BROADCAST 0x0020
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#define VTE_DRST_CRC_ERR 0x0040
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#define VTE_DRST_RUNT 0x0080
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#define VTE_DRST_LONG 0x0100
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#define VTE_DRST_TRUNC 0x0200
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#define VTE_DRST_DRIBBLE 0x0400
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#define VTE_DRST_PHY_ERR 0x0800
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#define VTE_DRST_RX_OK 0x4000
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#define VTE_DRST_RX_OWN 0x8000
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#define VTE_RX_LEN(x) ((x) & 0x7FF)
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#define VTE_RX_HIDX(x) ((x) & 0x3F)
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/*
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* TX descriptor
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* - Added one more uint32_t member to align it on 16 bytes boundary.
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*/
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struct vte_tx_desc {
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uint16_t dtst;
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uint16_t dtlen;
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uint32_t dtbp;
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uint32_t dtnp;
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uint32_t __pad; /* Not actual descriptor member. */
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};
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#define VTE_DTST_EXCESS_COL 0x0010
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#define VTE_DTST_LATE_COL 0x0020
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#define VTE_DTST_UNDERRUN 0x0040
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#define VTE_DTST_NO_CRC 0x2000
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#define VTE_DTST_TX_OK 0x4000
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#define VTE_DTST_TX_OWN 0x8000
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#define VTE_TX_LEN(x) ((x) & 0x7FF)
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#endif /* _IF_VTEREG_H */
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169
sys/dev/vte/if_vtevar.h
Normal file
169
sys/dev/vte/if_vtevar.h
Normal file
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/*-
|
||||
* Copyright (c) 2010, Pyun YongHyeon <yongari@FreeBSD.org>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice unmodified, this list of conditions, and the following
|
||||
* disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _IF_VTEVAR_H
|
||||
#define _IF_VTEVAR_H
|
||||
|
||||
#define VTE_TX_RING_CNT 64
|
||||
#define VTE_TX_RING_ALIGN 16
|
||||
/*
|
||||
* The TX/RX descriptor format has no limitation for number of
|
||||
* descriptors in TX/RX ring. However, the maximum number of
|
||||
* descriptors that could be set as RX descriptor ring residue
|
||||
* counter is 255. This effectively limits number of RX
|
||||
* descriptors available to be less than or equal to 255.
|
||||
*/
|
||||
#define VTE_RX_RING_CNT 128
|
||||
#define VTE_RX_RING_ALIGN 16
|
||||
#define VTE_RX_BUF_ALIGN 4
|
||||
|
||||
#define VTE_DESC_INC(x, y) ((x) = ((x) + 1) % (y))
|
||||
|
||||
#define VTE_TX_RING_SZ \
|
||||
(sizeof(struct vte_tx_desc) * VTE_TX_RING_CNT)
|
||||
#define VTE_RX_RING_SZ \
|
||||
(sizeof(struct vte_rx_desc) * VTE_RX_RING_CNT)
|
||||
|
||||
#define VTE_RX_BUF_SIZE_MAX (MCLBYTES - sizeof(uint32_t))
|
||||
|
||||
#define VTE_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
|
||||
|
||||
struct vte_rxdesc {
|
||||
struct mbuf *rx_m;
|
||||
bus_dmamap_t rx_dmamap;
|
||||
struct vte_rx_desc *rx_desc;
|
||||
};
|
||||
|
||||
struct vte_txdesc {
|
||||
struct mbuf *tx_m;
|
||||
bus_dmamap_t tx_dmamap;
|
||||
struct vte_tx_desc *tx_desc;
|
||||
int tx_flags;
|
||||
#define VTE_TXMBUF 0x0001
|
||||
};
|
||||
|
||||
struct vte_chain_data {
|
||||
bus_dma_tag_t vte_parent_tag;
|
||||
bus_dma_tag_t vte_buffer_tag;
|
||||
bus_dma_tag_t vte_tx_tag;
|
||||
struct vte_txdesc vte_txdesc[VTE_TX_RING_CNT];
|
||||
struct mbuf *vte_txmbufs[VTE_TX_RING_CNT];
|
||||
bus_dma_tag_t vte_rx_tag;
|
||||
struct vte_rxdesc vte_rxdesc[VTE_RX_RING_CNT];
|
||||
bus_dma_tag_t vte_tx_ring_tag;
|
||||
bus_dmamap_t vte_tx_ring_map;
|
||||
bus_dma_tag_t vte_rx_ring_tag;
|
||||
bus_dmamap_t vte_rx_ring_map;
|
||||
bus_dma_tag_t vte_rr_ring_tag;
|
||||
bus_dmamap_t vte_rr_ring_map;
|
||||
bus_dmamap_t vte_rx_sparemap;
|
||||
bus_dma_tag_t vte_cmb_tag;
|
||||
bus_dmamap_t vte_cmb_map;
|
||||
bus_dma_tag_t vte_smb_tag;
|
||||
bus_dmamap_t vte_smb_map;
|
||||
struct vte_tx_desc *vte_tx_ring;
|
||||
bus_addr_t vte_tx_ring_paddr;
|
||||
struct vte_rx_desc *vte_rx_ring;
|
||||
bus_addr_t vte_rx_ring_paddr;
|
||||
|
||||
int vte_tx_prod;
|
||||
int vte_tx_cons;
|
||||
int vte_tx_cnt;
|
||||
int vte_rx_cons;
|
||||
};
|
||||
|
||||
struct vte_hw_stats {
|
||||
/* RX stats. */
|
||||
uint32_t rx_frames;
|
||||
uint32_t rx_bcast_frames;
|
||||
uint32_t rx_mcast_frames;
|
||||
uint32_t rx_runts;
|
||||
uint32_t rx_crcerrs;
|
||||
uint32_t rx_long_frames;
|
||||
uint32_t rx_fifo_full;
|
||||
uint32_t rx_desc_unavail;
|
||||
uint32_t rx_pause_frames;
|
||||
|
||||
/* TX stats. */
|
||||
uint32_t tx_frames;
|
||||
uint32_t tx_underruns;
|
||||
uint32_t tx_late_colls;
|
||||
uint32_t tx_pause_frames;
|
||||
};
|
||||
|
||||
struct vte_ident {
|
||||
uint16_t vendorid;
|
||||
uint16_t deviceid;
|
||||
const char *name;
|
||||
};
|
||||
|
||||
/*
|
||||
* Software state per device.
|
||||
*/
|
||||
struct vte_softc {
|
||||
struct ifnet *vte_ifp;
|
||||
device_t vte_dev;
|
||||
device_t vte_miibus;
|
||||
struct resource *vte_res;
|
||||
int vte_res_id;
|
||||
int vte_res_type;
|
||||
struct resource *vte_irq;
|
||||
void *vte_intrhand;
|
||||
const struct vte_ident *vte_ident;
|
||||
uint8_t vte_eaddr[ETHER_ADDR_LEN];
|
||||
int vte_flags;
|
||||
#define VTE_FLAG_LINK 0x8000
|
||||
|
||||
struct callout vte_tick_ch;
|
||||
struct vte_hw_stats vte_stats;
|
||||
struct vte_chain_data vte_cdata;
|
||||
int vte_if_flags;
|
||||
int vte_watchdog_timer;
|
||||
int vte_int_rx_mod;
|
||||
int vte_int_tx_mod;
|
||||
|
||||
struct mtx vte_mtx;
|
||||
};
|
||||
|
||||
/* Register access macros. */
|
||||
#define CSR_WRITE_2(_sc, reg, val) \
|
||||
bus_write_2((_sc)->vte_res, (reg), (val))
|
||||
#define CSR_READ_2(_sc, reg) \
|
||||
bus_read_2((_sc)->vte_res, (reg))
|
||||
|
||||
#define VTE_LOCK(_sc) mtx_lock(&(_sc)->vte_mtx)
|
||||
#define VTE_UNLOCK(_sc) mtx_unlock(&(_sc)->vte_mtx)
|
||||
#define VTE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->vte_mtx, MA_OWNED)
|
||||
|
||||
#define VTE_TX_TIMEOUT 5
|
||||
#define VTE_RESET_TIMEOUT 100
|
||||
#define VTE_TIMEOUT 1000
|
||||
#define VTE_PHY_TIMEOUT 1000
|
||||
|
||||
#endif /* _IF_VTEVAR_H */
|
||||
|
|
@ -244,6 +244,7 @@ device tl # Texas Instruments ThunderLAN
|
|||
device tx # SMC EtherPower II (83c170 ``EPIC'')
|
||||
device vge # VIA VT612x gigabit Ethernet
|
||||
device vr # VIA Rhine, Rhine II
|
||||
device vte # DM&P Vortex86 RDC R6040 Fast Ethernet
|
||||
device wb # Winbond W89C840F
|
||||
device xl # 3Com 3c90x (``Boomerang'', ``Cyclone'')
|
||||
|
||||
|
|
|
|||
|
|
@ -305,6 +305,7 @@ SUBDIR= ${_3dfx} \
|
|||
vkbd \
|
||||
${_vpo} \
|
||||
vr \
|
||||
vte \
|
||||
vx \
|
||||
wb \
|
||||
${_wi} \
|
||||
|
|
|
|||
8
sys/modules/vte/Makefile
Normal file
8
sys/modules/vte/Makefile
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
# $FreeBSD$
|
||||
|
||||
.PATH: ${.CURDIR}/../../dev/vte
|
||||
|
||||
KMOD= if_vte
|
||||
SRCS= if_vte.c device_if.h bus_if.h pci_if.h miibus_if.h
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
Loading…
Reference in a new issue