From 2474dccf1ac74015e036e414760fa22c14f0eb4a Mon Sep 17 00:00:00 2001 From: "Bjoern A. Zeeb" Date: Fri, 13 May 2016 15:11:17 +0000 Subject: [PATCH] We already turn the AMD erratum383 workaround on for certain VM_GUEST_VM if specific CPU features are not present. Some simulation environments, e.g. gem5, have been found to require more TLB management from the kernel in certain setups. It is currently unclear why. Turning on the workaround_erratum383 seems to help and make problems (panics) go away. Given this is a fairly uncommon environment so far, allowing the workaround to be manually enabled from loader in order to make debugging and comparing traces easier, but also to allow gem5 run FreeBSD in X86 timing mode, seems to be the least intrusive option for now until the issue if fully understood. Sponsored by: DARPA/AFRL Reviewed by: kib, alc (earlier) MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D6206 --- sys/x86/x86/mca.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sys/x86/x86/mca.c b/sys/x86/x86/mca.c index c4ceef26f14..9347af2c660 100644 --- a/sys/x86/x86/mca.c +++ b/sys/x86/x86/mca.c @@ -104,7 +104,8 @@ SYSCTL_INT(_hw_mca, OID_AUTO, intel6h_HSD131, CTLFLAG_RDTUN, &intel6h_HSD131, 0, "Administrative toggle for logging of spurious corrected errors"); int workaround_erratum383; -SYSCTL_INT(_hw_mca, OID_AUTO, erratum383, CTLFLAG_RD, &workaround_erratum383, 0, +SYSCTL_INT(_hw_mca, OID_AUTO, erratum383, CTLFLAG_RD|CTLFLAG_RDTUN, + &workaround_erratum383, 0, "Is the workaround for Erratum 383 on AMD Family 10h processors enabled?"); static STAILQ_HEAD(, mca_internal) mca_freelist;