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Add more arm64 special register values

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These will be used to simplify the kernel special register handling.

Sponsored by:	Arm Ltd
This commit is contained in:
Andrew Turner 2023-06-09 18:46:58 +01:00
parent bb5d6d14d8
commit 178747a158
1 changed files with 16 additions and 0 deletions
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16
sys/arm64/include/armreg.h
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@ -1222,6 +1222,14 @@
#define MDSCR_MDE_SHIFT 15
#define MDSCR_MDE (UL(0x1) << MDSCR_MDE_SHIFT)
/* MIDR_EL1 - Main ID Register */
#define MIDR_EL1 MRS_REG(MIDR_EL1)
#define MIDR_EL1_op0 3
#define MIDR_EL1_op1 0
#define MIDR_EL1_CRn 0
#define MIDR_EL1_CRm 0
#define MIDR_EL1_op2 0
/* MPIDR_EL1 - Multiprocessor Affinity Register */
#define MPIDR_EL1 MRS_REG(MPIDR_EL1)
#define MPIDR_EL1_op0 3
@ -1861,6 +1869,14 @@
#define PSR_SETTABLE_32 PSR_FLAGS
#define PSR_SETTABLE_64 (PSR_FLAGS | PSR_SS)
/* REVIDR_EL1 - Revision ID Register */
#define REVIDR_EL1 MRS_REG(REVIDR_EL1)
#define REVIDR_EL1_op0 3
#define REVIDR_EL1_op1 0
#define REVIDR_EL1_CRn 0
#define REVIDR_EL1_CRm 0
#define REVIDR_EL1_op2 6
/* TCR_EL1 - Translation Control Register */
/* Bits 63:59 are reserved */
#define TCR_TCMA1_SHIFT 58