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Support PCI extended config space in bhyve.
Add the ACPI MCFG table to advertise the extended config memory window. Introduce a new flag MEM_F_IMMUTABLE for memory ranges that cannot be deleted or moved in the guest's address space. The PCI extended config space is an example of an immutable memory range. Add emulation for the "movzw" instruction. This instruction is used by FreeBSD to read a 16-bit extended config space register. CR: https://phabric.freebsd.org/D505 Reviewed by: jhb, grehan Requested by: tychon
This commit is contained in:
Neel Natu
parent
8f5a8818f5
commit
12a6eb99a1
6 changed files with 232 additions and 82 deletions
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@ -82,6 +82,10 @@ static const struct vie_op two_byte_opcodes[256] = {
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.op_byte = 0xB6,
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.op_type = VIE_OP_TYPE_MOVZX,
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},
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[0xB7] = {
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.op_byte = 0xB7,
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.op_type = VIE_OP_TYPE_MOVZX,
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},
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[0xBE] = {
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.op_byte = 0xBE,
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.op_type = VIE_OP_TYPE_MOVSX,
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@ -503,6 +507,25 @@ emulate_movx(void *vm, int vcpuid, uint64_t gpa, struct vie *vie,
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val = (uint8_t)val;
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/* write the result */
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error = vie_update_register(vm, vcpuid, reg, val, size);
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break;
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case 0xB7:
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/*
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* MOV and zero extend word from mem (ModRM:r/m) to
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* reg (ModRM:reg).
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*
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* 0F B7/r movzx r32, r/m16
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* REX.W + 0F B7/r movzx r64, r/m16
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*/
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error = memread(vm, vcpuid, gpa, &val, 2, arg);
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if (error)
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return (error);
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reg = gpr_map[vie->reg];
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/* zero-extend word */
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val = (uint16_t)val;
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error = vie_update_register(vm, vcpuid, reg, val, size);
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break;
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case 0xBE:
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@ -40,12 +40,13 @@
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* Layout
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* ------
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* RSDP -> 0xf2400 (36 bytes fixed)
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* RSDT -> 0xf2440 (36 bytes + 4*N table addrs, 2 used)
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* XSDT -> 0xf2480 (36 bytes + 8*N table addrs, 2 used)
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* RSDT -> 0xf2440 (36 bytes + 4*7 table addrs, 4 used)
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* XSDT -> 0xf2480 (36 bytes + 8*7 table addrs, 4 used)
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* MADT -> 0xf2500 (depends on #CPUs)
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* FADT -> 0xf2600 (268 bytes)
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* HPET -> 0xf2740 (56 bytes)
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* FACS -> 0xf2780 (64 bytes)
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* MCFG -> 0xf2780 (60 bytes)
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* FACS -> 0xf27C0 (64 bytes)
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* DSDT -> 0xf2800 (variable - can go up to 0x100000)
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*/
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@ -80,7 +81,8 @@ __FBSDID("$FreeBSD$");
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#define MADT_OFFSET 0x100
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#define FADT_OFFSET 0x200
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#define HPET_OFFSET 0x340
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#define FACS_OFFSET 0x380
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#define MCFG_OFFSET 0x380
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#define FACS_OFFSET 0x3C0
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#define DSDT_OFFSET 0x400
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#define BHYVE_ASL_TEMPLATE "bhyve.XXXXXXX"
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@ -178,6 +180,8 @@ basl_fwrite_rsdt(FILE *fp)
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basl_acpi_base + FADT_OFFSET);
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EFPRINTF(fp, "[0004]\t\tACPI Table Address 2 : %08X\n",
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basl_acpi_base + HPET_OFFSET);
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EFPRINTF(fp, "[0004]\t\tACPI Table Address 3 : %08X\n",
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basl_acpi_base + MCFG_OFFSET);
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EFFLUSH(fp);
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@ -216,6 +220,8 @@ basl_fwrite_xsdt(FILE *fp)
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basl_acpi_base + FADT_OFFSET);
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EFPRINTF(fp, "[0004]\t\tACPI Table Address 2 : 00000000%08X\n",
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basl_acpi_base + HPET_OFFSET);
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EFPRINTF(fp, "[0004]\t\tACPI Table Address 3 : 00000000%08X\n",
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basl_acpi_base + MCFG_OFFSET);
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EFFLUSH(fp);
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@ -582,6 +588,39 @@ err_exit:
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return (errno);
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}
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static int
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basl_fwrite_mcfg(FILE *fp)
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{
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int err = 0;
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EFPRINTF(fp, "/*\n");
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EFPRINTF(fp, " * bhyve MCFG template\n");
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EFPRINTF(fp, " */\n");
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EFPRINTF(fp, "[0004]\t\tSignature : \"MCFG\"\n");
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EFPRINTF(fp, "[0004]\t\tTable Length : 00000000\n");
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EFPRINTF(fp, "[0001]\t\tRevision : 01\n");
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EFPRINTF(fp, "[0001]\t\tChecksum : 00\n");
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EFPRINTF(fp, "[0006]\t\tOem ID : \"BHYVE \"\n");
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EFPRINTF(fp, "[0008]\t\tOem Table ID : \"BVMCFG \"\n");
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EFPRINTF(fp, "[0004]\t\tOem Revision : 00000001\n");
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/* iasl will fill in the compiler ID/revision fields */
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EFPRINTF(fp, "[0004]\t\tAsl Compiler ID : \"xxxx\"\n");
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EFPRINTF(fp, "[0004]\t\tAsl Compiler Revision : 00000000\n");
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EFPRINTF(fp, "[0008]\t\tReserved : 0\n");
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EFPRINTF(fp, "\n");
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EFPRINTF(fp, "[0008]\t\tBase Address : %016lX\n", pci_ecfg_base());
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EFPRINTF(fp, "[0002]\t\tSegment Group: 0000\n");
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EFPRINTF(fp, "[0001]\t\tStart Bus: 00\n");
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EFPRINTF(fp, "[0001]\t\tEnd Bus: FF\n");
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EFPRINTF(fp, "[0004]\t\tReserved : 0\n");
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EFFLUSH(fp);
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return (0);
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err_exit:
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return (errno);
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}
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static int
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basl_fwrite_facs(FILE *fp)
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{
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@ -921,6 +960,7 @@ static struct {
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{ basl_fwrite_madt, MADT_OFFSET },
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{ basl_fwrite_fadt, FADT_OFFSET },
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{ basl_fwrite_hpet, HPET_OFFSET },
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{ basl_fwrite_mcfg, MCFG_OFFSET },
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{ basl_fwrite_facs, FACS_OFFSET },
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{ basl_fwrite_dsdt, DSDT_OFFSET },
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{ NULL }
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@ -162,7 +162,7 @@ emulate_mem(struct vmctx *ctx, int vcpu, uint64_t paddr, struct vie *vie,
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{
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struct mmio_rb_range *entry;
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int err;
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int err, immutable;
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pthread_rwlock_rdlock(&mmio_rwlock);
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/*
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@ -186,9 +186,27 @@ emulate_mem(struct vmctx *ctx, int vcpu, uint64_t paddr, struct vie *vie,
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}
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assert(entry != NULL);
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/*
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* An 'immutable' memory range is guaranteed to be never removed
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* so there is no need to hold 'mmio_rwlock' while calling the
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* handler.
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*
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* XXX writes to the PCIR_COMMAND register can cause register_mem()
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* to be called. If the guest is using PCI extended config space
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* to modify the PCIR_COMMAND register then register_mem() can
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* deadlock on 'mmio_rwlock'. However by registering the extended
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* config space window as 'immutable' the deadlock can be avoided.
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*/
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immutable = (entry->mr_param.flags & MEM_F_IMMUTABLE);
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if (immutable)
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pthread_rwlock_unlock(&mmio_rwlock);
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err = vmm_emulate_instruction(ctx, vcpu, paddr, vie, paging,
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mem_read, mem_write, &entry->mr_param);
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pthread_rwlock_unlock(&mmio_rwlock);
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if (!immutable)
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pthread_rwlock_unlock(&mmio_rwlock);
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return (err);
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}
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@ -246,6 +264,7 @@ unregister_mem(struct mem_range *memp)
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mr = &entry->mr_param;
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assert(mr->name == memp->name);
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assert(mr->base == memp->base && mr->size == memp->size);
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assert((mr->flags & MEM_F_IMMUTABLE) == 0);
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RB_REMOVE(mmio_rb_tree, &mmio_rb_root, entry);
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/* flush Per-vCPU cache */
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@ -48,6 +48,7 @@ struct mem_range {
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#define MEM_F_READ 0x1
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#define MEM_F_WRITE 0x2
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#define MEM_F_RW 0x3
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#define MEM_F_IMMUTABLE 0x4 /* mem_range cannot be unregistered */
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void init_mem(void);
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int emulate_mem(struct vmctx *, int vcpu, uint64_t paddr, struct vie *vie,
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@ -109,16 +109,20 @@ static uint64_t pci_emul_membase64;
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#define PCI_EMUL_IOBASE 0x2000
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#define PCI_EMUL_IOLIMIT 0x10000
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#define PCI_EMUL_MEMLIMIT32 0xE0000000 /* 3.5GB */
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#define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */
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#define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */
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SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE);
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#define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE
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#define PCI_EMUL_MEMBASE64 0xD000000000UL
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#define PCI_EMUL_MEMLIMIT64 0xFD00000000UL
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static struct pci_devemu *pci_emul_finddev(char *name);
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static void pci_lintr_route(struct pci_devinst *pi);
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static void pci_lintr_update(struct pci_devinst *pi);
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static struct mem_range pci_mem_hole;
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static void pci_lintr_route(struct pci_devinst *pi);
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static void pci_lintr_update(struct pci_devinst *pi);
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static void pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot,
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int func, int coff, int bytes, uint32_t *val);
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/*
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* I/O access
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@ -1023,12 +1027,37 @@ pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
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return (0);
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}
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static int
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pci_emul_ecfg_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr,
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int bytes, uint64_t *val, void *arg1, long arg2)
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{
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int bus, slot, func, coff, in;
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coff = addr & 0xfff;
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func = (addr >> 12) & 0x7;
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slot = (addr >> 15) & 0x1f;
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bus = (addr >> 20) & 0xff;
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in = (dir == MEM_F_READ);
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if (in)
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*val = ~0UL;
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pci_cfgrw(ctx, vcpu, in, bus, slot, func, coff, bytes, (uint32_t *)val);
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return (0);
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}
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uint64_t
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pci_ecfg_base(void)
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{
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return (PCI_EMUL_ECFG_BASE);
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}
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#define BUSIO_ROUNDUP 32
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#define BUSMEM_ROUNDUP (1024 * 1024)
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int
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init_pci(struct vmctx *ctx)
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{
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struct mem_range mr;
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struct pci_devemu *pde;
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struct businfo *bi;
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struct slotinfo *si;
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@ -1112,22 +1141,34 @@ init_pci(struct vmctx *ctx)
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* The guest physical memory map looks like the following:
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* [0, lowmem) guest system memory
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* [lowmem, lowmem_limit) memory hole (may be absent)
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* [lowmem_limit, 4GB) PCI hole (32-bit BAR allocation)
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* [lowmem_limit, 0xE0000000) PCI hole (32-bit BAR allocation)
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* [0xE0000000, 0xF0000000) PCI extended config window
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* [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware
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* [4GB, 4GB + highmem)
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*
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*/
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/*
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* Accesses to memory addresses that are not allocated to system
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* memory or PCI devices return 0xff's.
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*/
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lowmem = vm_get_lowmem_size(ctx);
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bzero(&mr, sizeof(struct mem_range));
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mr.name = "PCI hole";
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mr.flags = MEM_F_RW | MEM_F_IMMUTABLE;
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mr.base = lowmem;
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mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem;
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mr.handler = pci_emul_fallback_handler;
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error = register_mem_fallback(&mr);
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assert(error == 0);
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memset(&pci_mem_hole, 0, sizeof(struct mem_range));
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pci_mem_hole.name = "PCI hole";
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pci_mem_hole.flags = MEM_F_RW;
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pci_mem_hole.base = lowmem;
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pci_mem_hole.size = (4ULL * 1024 * 1024 * 1024) - lowmem;
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pci_mem_hole.handler = pci_emul_fallback_handler;
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error = register_mem_fallback(&pci_mem_hole);
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/* PCI extended config space */
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bzero(&mr, sizeof(struct mem_range));
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mr.name = "PCI ECFG";
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mr.flags = MEM_F_RW | MEM_F_IMMUTABLE;
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mr.base = PCI_EMUL_ECFG_BASE;
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mr.size = PCI_EMUL_ECFG_SIZE;
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mr.handler = pci_emul_ecfg_handler;
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error = register_mem(&mr);
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assert(error == 0);
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return (0);
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@ -1612,41 +1653,6 @@ pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv)
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}
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}
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static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff;
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static int
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pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
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uint32_t *eax, void *arg)
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{
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uint32_t x;
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if (bytes != 4) {
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if (in)
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*eax = (bytes == 2) ? 0xffff : 0xff;
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return (0);
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}
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if (in) {
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x = (cfgbus << 16) |
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(cfgslot << 11) |
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(cfgfunc << 8) |
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cfgoff;
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if (cfgenable)
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x |= CONF1_ENABLE;
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*eax = x;
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} else {
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x = *eax;
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cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE;
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cfgoff = x & PCI_REGMAX;
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cfgfunc = (x >> 8) & PCI_FUNCMAX;
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cfgslot = (x >> 11) & PCI_SLOTMAX;
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cfgbus = (x >> 16) & PCI_BUSMAX;
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}
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return (0);
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}
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INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr);
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static uint32_t
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bits_changed(uint32_t old, uint32_t new, uint32_t mask)
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{
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@ -1709,41 +1715,51 @@ pci_emul_cmdwrite(struct pci_devinst *pi, uint32_t new, int bytes)
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pci_lintr_update(pi);
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}
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static int
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pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
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uint32_t *eax, void *arg)
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static void
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pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, int func,
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int coff, int bytes, uint32_t *eax)
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{
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struct businfo *bi;
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struct slotinfo *si;
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struct pci_devinst *pi;
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struct pci_devemu *pe;
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int coff, idx, needcfg;
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int idx, needcfg;
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uint64_t addr, bar, mask;
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assert(bytes == 1 || bytes == 2 || bytes == 4);
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if ((bi = pci_businfo[cfgbus]) != NULL) {
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si = &bi->slotinfo[cfgslot];
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pi = si->si_funcs[cfgfunc].fi_devi;
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if ((bi = pci_businfo[bus]) != NULL) {
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si = &bi->slotinfo[slot];
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pi = si->si_funcs[func].fi_devi;
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} else
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pi = NULL;
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coff = cfgoff + (port - CONF1_DATA_PORT);
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#if 0
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printf("pcicfg-%s from 0x%0x of %d bytes (%d/%d/%d)\n\r",
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in ? "read" : "write", coff, bytes, cfgbus, cfgslot, cfgfunc);
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#endif
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/*
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* Just return if there is no device at this cfgslot:cfgfunc,
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* if the guest is doing an un-aligned access, or if the config
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* address word isn't enabled.
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* Just return if there is no device at this slot:func or if the
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* the guest is doing an un-aligned access.
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*/
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if (!cfgenable || pi == NULL || (coff & (bytes - 1)) != 0) {
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if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) ||
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(coff & (bytes - 1)) != 0) {
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if (in)
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*eax = 0xffffffff;
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return (0);
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return;
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}
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/*
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* Ignore all writes beyond the standard config space and return all
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* ones on reads.
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*/
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if (coff >= PCI_REGMAX + 1) {
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if (in) {
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*eax = 0xffffffff;
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/*
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* Extended capabilities begin at offset 256 in config
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* space. Absence of extended capabilities is signaled
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* with all 0s in the extended capability header at
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* offset 256.
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*/
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if (coff <= PCI_REGMAX + 4)
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*eax = 0x00000000;
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}
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return;
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}
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pe = pi->pi_d;
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@ -1754,8 +1770,8 @@ pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
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if (in) {
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/* Let the device emulation override the default handler */
|
||||
if (pe->pe_cfgread != NULL) {
|
||||
needcfg = pe->pe_cfgread(ctx, vcpu, pi,
|
||||
coff, bytes, eax);
|
||||
needcfg = pe->pe_cfgread(ctx, vcpu, pi, coff, bytes,
|
||||
eax);
|
||||
} else {
|
||||
needcfg = 1;
|
||||
}
|
||||
|
|
@ -1769,12 +1785,12 @@ pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
|
|||
*eax = pci_get_cfgdata32(pi, coff);
|
||||
}
|
||||
|
||||
pci_emul_hdrtype_fixup(cfgbus, cfgslot, coff, bytes, eax);
|
||||
pci_emul_hdrtype_fixup(bus, slot, coff, bytes, eax);
|
||||
} else {
|
||||
/* Let the device emulation override the default handler */
|
||||
if (pe->pe_cfgwrite != NULL &&
|
||||
(*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0)
|
||||
return (0);
|
||||
return;
|
||||
|
||||
/*
|
||||
* Special handling for write to BAR registers
|
||||
|
|
@ -1785,7 +1801,7 @@ pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
|
|||
* 4-byte aligned.
|
||||
*/
|
||||
if (bytes != 4 || (coff & 0x3) != 0)
|
||||
return (0);
|
||||
return;
|
||||
idx = (coff - PCIR_BAR(0)) / 4;
|
||||
mask = ~(pi->pi_bar[idx].size - 1);
|
||||
switch (pi->pi_bar[idx].type) {
|
||||
|
|
@ -1843,7 +1859,57 @@ pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
|
|||
CFGWRITE(pi, coff, *eax, bytes);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff;
|
||||
|
||||
static int
|
||||
pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
|
||||
uint32_t *eax, void *arg)
|
||||
{
|
||||
uint32_t x;
|
||||
|
||||
if (bytes != 4) {
|
||||
if (in)
|
||||
*eax = (bytes == 2) ? 0xffff : 0xff;
|
||||
return (0);
|
||||
}
|
||||
|
||||
if (in) {
|
||||
x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff;
|
||||
if (cfgenable)
|
||||
x |= CONF1_ENABLE;
|
||||
*eax = x;
|
||||
} else {
|
||||
x = *eax;
|
||||
cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE;
|
||||
cfgoff = x & PCI_REGMAX;
|
||||
cfgfunc = (x >> 8) & PCI_FUNCMAX;
|
||||
cfgslot = (x >> 11) & PCI_SLOTMAX;
|
||||
cfgbus = (x >> 16) & PCI_BUSMAX;
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr);
|
||||
|
||||
static int
|
||||
pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
|
||||
uint32_t *eax, void *arg)
|
||||
{
|
||||
int coff;
|
||||
|
||||
assert(bytes == 1 || bytes == 2 || bytes == 4);
|
||||
|
||||
coff = cfgoff + (port - CONF1_DATA_PORT);
|
||||
if (cfgenable) {
|
||||
pci_cfgrw(ctx, vcpu, in, cfgbus, cfgslot, cfgfunc, coff, bytes,
|
||||
eax);
|
||||
} else {
|
||||
/* Ignore accesses to cfgdata if not enabled by cfgaddr */
|
||||
if (in)
|
||||
*eax = 0xffffffff;
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -235,6 +235,7 @@ uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size);
|
|||
int pci_count_lintr(int bus);
|
||||
void pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg);
|
||||
void pci_write_dsdt(void);
|
||||
uint64_t pci_ecfg_base(void);
|
||||
int pci_bus_configured(int bus);
|
||||
|
||||
static __inline void
|
||||
|
|
|
|||
Loading…
Reference in a new issue