From 10e71e226056600fbc6bcceaeabc2d974e4c6b85 Mon Sep 17 00:00:00 2001 From: Pyun YongHyeon Date: Mon, 23 May 2011 19:58:08 +0000 Subject: [PATCH] Do not blindly clear entire GPHY control register. It seems some bits of the register is used for other purposes such that clearing these bits resulted in unexpected results such as corrupted RX frames or missing LE status updates. For old controllers like Yukon EC it had no effect but it caused all kind of troubles on Yukon Supreme. This change shall improve stability of controllers like Yukon Ultra, Ultra2, Extreme, Optima and Supreme. --- sys/dev/msk/if_msk.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sys/dev/msk/if_msk.c b/sys/dev/msk/if_msk.c index 3af1b205fda..8dc2d30d823 100644 --- a/sys/dev/msk/if_msk.c +++ b/sys/dev/msk/if_msk.c @@ -1362,8 +1362,8 @@ mskc_reset(struct msk_softc *sc) /* Reset GPHY/GMAC Control */ for (i = 0; i < sc->msk_num_port; i++) { /* GPHY Control reset. */ - CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); - CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); + CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); + CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); /* GMAC Control reset. */ CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR);