From 0dc487341e352e2ac9f3c15459d751a4424ecf6e Mon Sep 17 00:00:00 2001 From: Marius Strobl Date: Tue, 4 Apr 2006 21:00:44 +0000 Subject: [PATCH] For USIII CPUs the type of the trap caused by peeking/poking non-existent PCI devices apparently was changed from a special deferred trap with TPC pointing to the membar #Sync following the failing load/store instruction to a precise trap with TPC pointing to the failing load/store instruction. Thus remove the check the check whether TPC points to a membar #Sync in case of a data access trap as it's off-by-one for USIII CPUs and it should be sufficient to check whether the trap happend while in fasword*() to properly detect traps caused by peeking/poking. This also corresponds to what other OSs do. Note that also only the USIIi manual suggests to check the TPC for such traps while the USII one doesn't (in the public USIII manual device peeking/poking isn't mentioned at all). --- sys/sparc64/sparc64/trap.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/sys/sparc64/sparc64/trap.c b/sys/sparc64/sparc64/trap.c index 4cbbbad9b0b..4d623a4c05f 100644 --- a/sys/sparc64/sparc64/trap.c +++ b/sys/sparc64/sparc64/trap.c @@ -354,14 +354,13 @@ trap(struct trapframe *tf) break; case T_DATA_ERROR: /* - * handle PCI poke/peek as per UltraSPARC IIi - * User's Manual 16.2.1. + * Handle PCI poke/peek as per UltraSPARC IIi + * User's Manual 16.2.1, modulo checking the + * TPC as USIII CPUs generate a precise trap + * instead of a special deferred one. */ -#define MEMBARSYNC_INST ((u_int32_t)0x8143e040) if (tf->tf_tpc > (u_long)fas_nofault_begin && - tf->tf_tpc < (u_long)fas_nofault_end && - *(u_int32_t *)tf->tf_tpc == MEMBARSYNC_INST && - ((u_int32_t *)tf->tf_tpc)[-2] == MEMBARSYNC_INST) { + tf->tf_tpc < (u_long)fas_nofault_end) { cache_flush(); cache_enable(); tf->tf_tpc = (u_long)fas_fault; @@ -369,7 +368,6 @@ trap(struct trapframe *tf) error = 0; break; } -#undef MEMBARSYNC_INST error = 1; break; default: