mirror of
https://github.com/opnsense/src.git
synced 2026-06-11 09:41:03 -04:00
Simplify the radeon microcode loading.
Submitted by: Christoph Mallon MFC after: 3 days
This commit is contained in:
Robert Noland
parent
b0d8ed7ad3
commit
0351ecf9e4
2 changed files with 135 additions and 216 deletions
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@ -282,6 +282,8 @@ static void r600_vm_init(struct drm_device *dev)
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/* load r600 microcode */
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static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
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{
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const u32 (*cp)[3];
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const u32 *pfp;
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int i;
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r600_do_cp_stop(dev_priv);
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@ -298,116 +300,60 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
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RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
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if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600)) {
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DRM_INFO("Loading R600 CP Microcode\n");
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for (i = 0; i < PM4_UCODE_SIZE; i++) {
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RADEON_WRITE(R600_CP_ME_RAM_DATA,
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R600_cp_microcode[i][0]);
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RADEON_WRITE(R600_CP_ME_RAM_DATA,
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R600_cp_microcode[i][1]);
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RADEON_WRITE(R600_CP_ME_RAM_DATA,
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R600_cp_microcode[i][2]);
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}
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RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
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DRM_INFO("Loading R600 PFP Microcode\n");
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for (i = 0; i < PFP_UCODE_SIZE; i++)
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RADEON_WRITE(R600_CP_PFP_UCODE_DATA, R600_pfp_microcode[i]);
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} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610)) {
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DRM_INFO("Loading RV610 CP Microcode\n");
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for (i = 0; i < PM4_UCODE_SIZE; i++) {
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RADEON_WRITE(R600_CP_ME_RAM_DATA,
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RV610_cp_microcode[i][0]);
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RADEON_WRITE(R600_CP_ME_RAM_DATA,
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RV610_cp_microcode[i][1]);
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RADEON_WRITE(R600_CP_ME_RAM_DATA,
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RV610_cp_microcode[i][2]);
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}
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RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
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DRM_INFO("Loading RV610 PFP Microcode\n");
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for (i = 0; i < PFP_UCODE_SIZE; i++)
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RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV610_pfp_microcode[i]);
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} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
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DRM_INFO("Loading RV630 CP Microcode\n");
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for (i = 0; i < PM4_UCODE_SIZE; i++) {
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RADEON_WRITE(R600_CP_ME_RAM_DATA,
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RV630_cp_microcode[i][0]);
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RADEON_WRITE(R600_CP_ME_RAM_DATA,
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RV630_cp_microcode[i][1]);
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RADEON_WRITE(R600_CP_ME_RAM_DATA,
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RV630_cp_microcode[i][2]);
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}
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RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
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DRM_INFO("Loading RV630 PFP Microcode\n");
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for (i = 0; i < PFP_UCODE_SIZE; i++)
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RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV630_pfp_microcode[i]);
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} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620)) {
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DRM_INFO("Loading RV620 CP Microcode\n");
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for (i = 0; i < PM4_UCODE_SIZE; i++) {
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RADEON_WRITE(R600_CP_ME_RAM_DATA,
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RV620_cp_microcode[i][0]);
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RADEON_WRITE(R600_CP_ME_RAM_DATA,
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RV620_cp_microcode[i][1]);
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RADEON_WRITE(R600_CP_ME_RAM_DATA,
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RV620_cp_microcode[i][2]);
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}
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RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
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DRM_INFO("Loading RV620 PFP Microcode\n");
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for (i = 0; i < PFP_UCODE_SIZE; i++)
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RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV620_pfp_microcode[i]);
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} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
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DRM_INFO("Loading RV635 CP Microcode\n");
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for (i = 0; i < PM4_UCODE_SIZE; i++) {
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RADEON_WRITE(R600_CP_ME_RAM_DATA,
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RV635_cp_microcode[i][0]);
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RADEON_WRITE(R600_CP_ME_RAM_DATA,
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RV635_cp_microcode[i][1]);
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RADEON_WRITE(R600_CP_ME_RAM_DATA,
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RV635_cp_microcode[i][2]);
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}
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RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
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DRM_INFO("Loading RV635 PFP Microcode\n");
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for (i = 0; i < PFP_UCODE_SIZE; i++)
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RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV635_pfp_microcode[i]);
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} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)) {
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DRM_INFO("Loading RV670 CP Microcode\n");
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for (i = 0; i < PM4_UCODE_SIZE; i++) {
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RADEON_WRITE(R600_CP_ME_RAM_DATA,
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RV670_cp_microcode[i][0]);
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RADEON_WRITE(R600_CP_ME_RAM_DATA,
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RV670_cp_microcode[i][1]);
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RADEON_WRITE(R600_CP_ME_RAM_DATA,
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RV670_cp_microcode[i][2]);
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}
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RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
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DRM_INFO("Loading RV670 PFP Microcode\n");
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for (i = 0; i < PFP_UCODE_SIZE; i++)
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RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV670_pfp_microcode[i]);
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} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780)) {
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DRM_INFO("Loading RS780 CP Microcode\n");
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for (i = 0; i < PM4_UCODE_SIZE; i++) {
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RADEON_WRITE(R600_CP_ME_RAM_DATA,
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RS780_cp_microcode[i][0]);
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RADEON_WRITE(R600_CP_ME_RAM_DATA,
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RS780_cp_microcode[i][1]);
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RADEON_WRITE(R600_CP_ME_RAM_DATA,
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RS780_cp_microcode[i][2]);
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}
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RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
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DRM_INFO("Loading RS780 PFP Microcode\n");
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for (i = 0; i < PFP_UCODE_SIZE; i++)
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RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RS780_pfp_microcode[i]);
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switch (dev_priv->flags & RADEON_FAMILY_MASK) {
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case CHIP_R600:
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DRM_INFO("Loading R600 Microcode\n");
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cp = R600_cp_microcode;
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pfp = R600_pfp_microcode;
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break;
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case CHIP_RV610:
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DRM_INFO("Loading RV610 Microcode\n");
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cp = RV610_cp_microcode;
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pfp = RV610_pfp_microcode;
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break;
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case CHIP_RV630:
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DRM_INFO("Loading RV630 Microcode\n");
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cp = RV630_cp_microcode;
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pfp = RV630_pfp_microcode;
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break;
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case CHIP_RV620:
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DRM_INFO("Loading RV620 Microcode\n");
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cp = RV620_cp_microcode;
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pfp = RV620_pfp_microcode;
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break;
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case CHIP_RV635:
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DRM_INFO("Loading RV635 Microcode\n");
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cp = RV635_cp_microcode;
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pfp = RV635_pfp_microcode;
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break;
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case CHIP_RV670:
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DRM_INFO("Loading RV670 Microcode\n");
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cp = RV670_cp_microcode;
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pfp = RV670_pfp_microcode;
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break;
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case CHIP_RS780:
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DRM_INFO("Loading RS780 Microcode\n");
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cp = RS780_cp_microcode;
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pfp = RS780_pfp_microcode;
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break;
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default:
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goto no_microcode;
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}
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for (i = 0; i != PM4_UCODE_SIZE; i++) {
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RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][0]);
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RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][1]);
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RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][2]);
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}
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RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
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for (i = 0; i != PFP_UCODE_SIZE; i++)
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RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]);
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no_microcode:;
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RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
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RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
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RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
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}
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static void r700_vm_init(struct drm_device *dev)
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@ -465,6 +411,8 @@ static void r700_vm_init(struct drm_device *dev)
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/* load r600 microcode */
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static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
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{
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const u32 *pfp;
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const u32 *cp;
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int i;
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r600_do_cp_stop(dev_priv);
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@ -479,51 +427,40 @@ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
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DRM_UDELAY(15000);
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RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
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if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)) {
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RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
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DRM_INFO("Loading RV770 PFP Microcode\n");
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for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
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RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV770_pfp_microcode[i]);
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RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
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RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
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DRM_INFO("Loading RV770 CP Microcode\n");
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for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
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RADEON_WRITE(R600_CP_ME_RAM_DATA, RV770_cp_microcode[i]);
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RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
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} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV730)) {
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RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
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DRM_INFO("Loading RV730 PFP Microcode\n");
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for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
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RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV730_pfp_microcode[i]);
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RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
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RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
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DRM_INFO("Loading RV730 CP Microcode\n");
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for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
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RADEON_WRITE(R600_CP_ME_RAM_DATA, RV730_cp_microcode[i]);
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RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
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} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)) {
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RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
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DRM_INFO("Loading RV710 PFP Microcode\n");
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for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
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RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV710_pfp_microcode[i]);
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RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
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RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
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DRM_INFO("Loading RV710 CP Microcode\n");
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for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
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RADEON_WRITE(R600_CP_ME_RAM_DATA, RV710_cp_microcode[i]);
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RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
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switch (dev_priv->flags & RADEON_FAMILY_MASK) {
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case CHIP_RV770:
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DRM_INFO("Loading RV770 Microcode\n");
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pfp = RV770_pfp_microcode;
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cp = RV770_cp_microcode;
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break;
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case CHIP_RV730:
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DRM_INFO("Loading RV730 Microcode\n");
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pfp = RV730_pfp_microcode;
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cp = RV730_cp_microcode;
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break;
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case CHIP_RV710:
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DRM_INFO("Loading RV710 Microcode\n");
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pfp = RV710_pfp_microcode;
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cp = RV710_cp_microcode;
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break;
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default:
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goto no_microcode;
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}
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RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
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for (i = 0; i != R700_PFP_UCODE_SIZE; i++)
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RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]);
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RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
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RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
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for (i = 0; i != R700_PM4_UCODE_SIZE; i++)
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RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i]);
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RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
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no_microcode:;
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RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
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RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
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RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
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}
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static void r600_test_writeback(drm_radeon_private_t *dev_priv)
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@ -455,88 +455,70 @@ static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
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/* Load the microcode for the CP */
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static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
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{
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const u32 (*cp)[2];
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int i;
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DRM_DEBUG("\n");
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radeon_do_wait_for_idle(dev_priv);
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RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
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if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
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switch (dev_priv->flags & RADEON_FAMILY_MASK) {
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case CHIP_R100:
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case CHIP_RV100:
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case CHIP_RV200:
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case CHIP_RS100:
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case CHIP_RS200:
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DRM_INFO("Loading R100 Microcode\n");
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for (i = 0; i < 256; i++) {
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RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
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R100_cp_microcode[i][1]);
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RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
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R100_cp_microcode[i][0]);
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}
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} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
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cp = R100_cp_microcode;
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break;
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case CHIP_R200:
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case CHIP_RV250:
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case CHIP_RV280:
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case CHIP_RS300:
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DRM_INFO("Loading R200 Microcode\n");
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for (i = 0; i < 256; i++) {
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RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
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R200_cp_microcode[i][1]);
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RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
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R200_cp_microcode[i][0]);
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}
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} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
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cp = R200_cp_microcode;
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break;
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case CHIP_R300:
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case CHIP_R350:
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case CHIP_RV350:
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case CHIP_RV380:
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case CHIP_RS400:
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case CHIP_RS480:
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DRM_INFO("Loading R300 Microcode\n");
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for (i = 0; i < 256; i++) {
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RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
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R300_cp_microcode[i][1]);
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RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
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R300_cp_microcode[i][0]);
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}
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} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
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cp = R300_cp_microcode;
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break;
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case CHIP_R420:
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case CHIP_R423:
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case CHIP_RV410:
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DRM_INFO("Loading R400 Microcode\n");
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for (i = 0; i < 256; i++) {
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RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
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R420_cp_microcode[i][1]);
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RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
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R420_cp_microcode[i][0]);
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}
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} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
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((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
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cp = R420_cp_microcode;
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break;
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case CHIP_RS690:
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case CHIP_RS740:
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DRM_INFO("Loading RS690/RS740 Microcode\n");
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for (i = 0; i < 256; i++) {
|
||||
RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
|
||||
RS690_cp_microcode[i][1]);
|
||||
RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
|
||||
RS690_cp_microcode[i][0]);
|
||||
}
|
||||
} else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
|
||||
cp = RS690_cp_microcode;
|
||||
break;
|
||||
case CHIP_RS600:
|
||||
DRM_INFO("Loading RS600 Microcode\n");
|
||||
for (i = 0; i < 256; i++) {
|
||||
RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
|
||||
RS600_cp_microcode[i][1]);
|
||||
RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
|
||||
RS600_cp_microcode[i][0]);
|
||||
}
|
||||
} else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
|
||||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
|
||||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
|
||||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
|
||||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
|
||||
((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
|
||||
cp = RS600_cp_microcode;
|
||||
break;
|
||||
case CHIP_RV515:
|
||||
case CHIP_R520:
|
||||
case CHIP_RV530:
|
||||
case CHIP_R580:
|
||||
case CHIP_RV560:
|
||||
case CHIP_RV570:
|
||||
DRM_INFO("Loading R500 Microcode\n");
|
||||
for (i = 0; i < 256; i++) {
|
||||
RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
|
||||
R520_cp_microcode[i][1]);
|
||||
RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
|
||||
R520_cp_microcode[i][0]);
|
||||
}
|
||||
cp = R520_cp_microcode;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
for (i = 0; i != 256; i++) {
|
||||
RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, cp[i][1]);
|
||||
RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, cp[i][0]);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue