mirror of
https://github.com/opnsense/src.git
synced 2026-06-09 08:43:19 -04:00
Adds the untouched code from the RMI 6.4 stuff.
This has a security device and the gig ethernet device. Note the 10gig device driver is yet missing.
This commit is contained in:
Randall Stewart
parent
b398a6322f
commit
022e93cf87
9 changed files with 12309 additions and 0 deletions
3066
sys/dev/rmi/sec/desc.h
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3066
sys/dev/rmi/sec/desc.h
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3193
sys/dev/rmi/sec/rmilib.c
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sys/dev/rmi/sec/rmilib.c
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sys/dev/rmi/sec/rmilib.h
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sys/dev/rmi/sec/rmilib.h
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@ -0,0 +1,991 @@
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/*-
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* Copyright (c) 2003-2009 RMI Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of RMI Corporation, nor the names of its contributors,
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RMI_BSD */
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#ifndef _RMILIB_H_
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#define _RMILIB_H_
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#include <dev/rmi/sec/desc.h>
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#include <mips/xlr/iomap.h>
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/*#define XLR_SEC_CMD_DEBUG*/
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#ifdef XLR_SEC_CMD_DEBUG
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#define DPRINT printf
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#define XLR_SEC_CMD_DIAG(fmt, args...) { \
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DPRINT(fmt, ##args); \
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}
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#define XLR_SEC_CMD_DIAG_SYM_DESC(desc, vec) { \
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decode_symkey_desc ((desc), (vec)); \
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}
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#else
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#define DPRINT(fmt, args...)
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#define XLR_SEC_CMD_DIAG(fmt, args...)
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#define XLR_SEC_CMD_DIAG_SYM_DESC(desc, vec)
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#endif
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/*
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#include <mips/include/pmap.h>
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#define OS_ALLOC_KERNEL(size) kmalloc((size), GFP_KERNEL)
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#define virt_to_phys(x) vtophys((vm_offset_t)(x))
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*/
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/*
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* Cryptographic parameter definitions
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*/
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#define XLR_SEC_DES_KEY_LENGTH 8 /* Bytes */
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#define XLR_SEC_3DES_KEY_LENGTH 24 /* Bytes */
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#define XLR_SEC_AES128_KEY_LENGTH 16 /* Bytes */
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#define XLR_SEC_AES192_KEY_LENGTH 24 /* Bytes */
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#define XLR_SEC_AES256_KEY_LENGTH 32 /* Bytes */
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#define XLR_SEC_AES128F8_KEY_LENGTH 32 /* Bytes */
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#define XLR_SEC_AES192F8_KEY_LENGTH 48 /* Bytes */
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#define XLR_SEC_AES256F8_KEY_LENGTH 64 /* Bytes */
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#define XLR_SEC_KASUMI_F8_KEY_LENGTH 16 /* Bytes */
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#define XLR_SEC_MAX_CRYPT_KEY_LENGTH XLR_SEC_AES256F8_KEY_LENGTH
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#define XLR_SEC_DES_IV_LENGTH 8 /* Bytes */
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#define XLR_SEC_AES_IV_LENGTH 16 /* Bytes */
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#define XLR_SEC_ARC4_IV_LENGTH 0 /* Bytes */
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#define XLR_SEC_KASUMI_F8_IV_LENGTH 16 /* Bytes */
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#define XLR_SEC_MAX_IV_LENGTH 16 /* Bytes */
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#define XLR_SEC_IV_LENGTH_BYTES 8 /* Bytes */
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#define XLR_SEC_AES_BLOCK_SIZE 16 /* Bytes */
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#define XLR_SEC_DES_BLOCK_SIZE 8 /* Bytes */
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#define XLR_SEC_3DES_BLOCK_SIZE 8 /* Bytes */
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#define XLR_SEC_MD5_BLOCK_SIZE 64 /* Bytes */
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#define XLR_SEC_SHA1_BLOCK_SIZE 64 /* Bytes */
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#define XLR_SEC_SHA256_BLOCK_SIZE 64 /* Bytes */
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#define XLR_SEC_SHA384_BLOCK_SIZE 128/* Bytes */
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#define XLR_SEC_SHA512_BLOCK_SIZE 128/* Bytes */
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#define XLR_SEC_GCM_BLOCK_SIZE 16 /* XXX: Bytes */
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#define XLR_SEC_KASUMI_F9_BLOCK_SIZE 16 /* XXX: Bytes */
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#define XLR_SEC_MAX_BLOCK_SIZE 64 /* Max of MD5/SHA */
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#define XLR_SEC_MD5_LENGTH 16 /* Bytes */
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#define XLR_SEC_SHA1_LENGTH 20 /* Bytes */
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#define XLR_SEC_SHA256_LENGTH 32 /* Bytes */
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#define XLR_SEC_SHA384_LENGTH 64 /* Bytes */
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#define XLR_SEC_SHA512_LENGTH 64 /* Bytes */
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#define XLR_SEC_GCM_LENGTH 16 /* Bytes */
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#define XLR_SEC_KASUMI_F9_LENGTH 16 /* Bytes */
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#define XLR_SEC_KASUMI_F9_RESULT_LENGTH 4 /* Bytes */
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#define XLR_SEC_HMAC_LENGTH 64 /* Max of MD5/SHA/SHA256 */
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#define XLR_SEC_MAX_AUTH_KEY_LENGTH XLR_SEC_SHA512_BLOCK_SIZE
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#define XLR_SEC_MAX_RC4_STATE_SIZE 264 /* char s[256], int i, int j */
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/* Status code is used by the SRL to indicate status */
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typedef unsigned int xlr_sec_status_t;
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/*
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* Status codes
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*/
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#define XLR_SEC_STATUS_SUCCESS 0
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#define XLR_SEC_STATUS_NO_DEVICE -1
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#define XLR_SEC_STATUS_TIMEOUT -2
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#define XLR_SEC_STATUS_INVALID_PARAMETER -3
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#define XLR_SEC_STATUS_DEVICE_FAILED -4
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#define XLR_SEC_STATUS_DEVICE_BUSY -5
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#define XLR_SEC_STATUS_NO_RESOURCE -6
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#define XLR_SEC_STATUS_CANCELLED -7
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/*
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* Flags
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*/
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#define XLR_SEC_FLAGS_HIGH_PRIORITY 1
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/* Error code is used to indicate any errors */
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typedef int xlr_sec_error_t;
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/*
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*/
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#define XLR_SEC_ERR_NONE 0
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#define XLR_SEC_ERR_CIPHER_OP -1
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#define XLR_SEC_ERR_CIPHER_TYPE -2
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#define XLR_SEC_ERR_CIPHER_MODE -3
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#define XLR_SEC_ERR_CIPHER_INIT -4
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#define XLR_SEC_ERR_DIGEST_TYPE -5
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#define XLR_SEC_ERR_DIGEST_INIT -6
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#define XLR_SEC_ERR_DIGEST_SRC -7
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#define XLR_SEC_ERR_CKSUM_TYPE -8
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#define XLR_SEC_ERR_CKSUM_SRC -9
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#define XLR_SEC_ERR_ALLOC -10
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#define XLR_SEC_ERR_CONTROL_VECTOR -11
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#define XLR_SEC_ERR_LOADHMACKEY_MODE -12
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#define XLR_SEC_ERR_PADHASH_MODE -13
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#define XLR_SEC_ERR_HASHBYTES_MODE -14
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#define XLR_SEC_ERR_NEXT_MODE -15
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#define XLR_SEC_ERR_PKT_IV_MODE -16
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#define XLR_SEC_ERR_LASTWORD_MODE -17
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#define XLR_SEC_ERR_PUBKEY_OP -18
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#define XLR_SEC_ERR_SYMKEY_MSGSND -19
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#define XLR_SEC_ERR_PUBKEY_MSGSND -20
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#define XLR_SEC_ERR_SYMKEY_GETSEM -21
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#define XLR_SEC_ERR_PUBKEY_GETSEM -22
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/*
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* Descriptor Vector quantities
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* (helps to identify descriptor type per operation)
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*/
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#define XLR_SEC_VECTOR_CIPHER_DES 0x0001
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#define XLR_SEC_VECTOR_CIPHER_3DES 0x0002
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#define XLR_SEC_VECTOR_CIPHER_AES128 0x0004
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#define XLR_SEC_VECTOR_CIPHER_AES192 0x0008
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#define XLR_SEC_VECTOR_CIPHER_AES256 0x0010
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#define XLR_SEC_VECTOR_CIPHER_ARC4 0x0020
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#define XLR_SEC_VECTOR_CIPHER_AES (XLR_SEC_VECTOR_CIPHER_AES128 | \
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XLR_SEC_VECTOR_CIPHER_AES192 | \
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XLR_SEC_VECTOR_CIPHER_AES256)
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#define XLR_SEC_VECTOR_CIPHER (XLR_SEC_VECTOR_CIPHER_DES | \
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XLR_SEC_VECTOR_CIPHER_3DES | \
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XLR_SEC_VECTOR_CIPHER_AES128 | \
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XLR_SEC_VECTOR_CIPHER_AES192 | \
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XLR_SEC_VECTOR_CIPHER_AES256 | \
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XLR_SEC_VECTOR_CIPHER_ARC4)
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#define XLR_SEC_VECTOR_HMAC 0x0040
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#define XLR_SEC_VECTOR_MAC 0x0080
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#define XLR_SEC_VECTOR_MODE_CTR_CFB 0x0100
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#define XLR_SEC_VECTOR_MODE_ECB_CBC_OFB 0x0200
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#define XLR_SEC_VECTOR_MODE_ECB_CBC 0x0400
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#define XLR_SEC_VECTOR_STATE 0x0800
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#define XLR_SEC_VECTOR_CIPHER_KASUMI_F8 0x01000
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#define XLR_SEC_VECTOR_HMAC2 0x02000
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#define XLR_SEC_VECTOR_GCM 0x04000
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#define XLR_SEC_VECTOR_F9 0x08000
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#define XLR_SEC_VECTOR_MODE_F8 0x10000
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#define XLR_SEC_VECTOR_CIPHER_ARC4__HMAC \
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(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_HMAC)
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#define XLR_SEC_VECTOR_CIPHER_ARC4__STATE \
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(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_STATE)
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#define XLR_SEC_VECTOR_CIPHER_ARC4__HMAC__STATE \
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(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_STATE)
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#define XLR_SEC_VECTOR__CIPHER_DES__HMAC__MODE_ECB_CBC \
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(XLR_SEC_VECTOR_CIPHER_DES | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_ECB_CBC)
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#define XLR_SEC_VECTOR__CIPHER_DES__MODE_ECB_CBC \
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(XLR_SEC_VECTOR_CIPHER_DES | XLR_SEC_VECTOR_MODE_ECB_CBC)
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#define XLR_SEC_VECTOR__CIPHER_3DES__HMAC__MODE_ECB_CBC \
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(XLR_SEC_VECTOR_CIPHER_3DES | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_ECB_CBC)
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#define XLR_SEC_VECTOR__CIPHER_3DES__MODE_ECB_CBC \
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(XLR_SEC_VECTOR_CIPHER_3DES | XLR_SEC_VECTOR_MODE_ECB_CBC)
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#define XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_CTR_CFB \
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(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_CTR_CFB)
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#define XLR_SEC_VECTOR__CIPHER_AES128__MODE_CTR_CFB \
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(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_MODE_CTR_CFB)
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#define XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_ECB_CBC_OFB \
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(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
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#define XLR_SEC_VECTOR__CIPHER_AES128__MODE_ECB_CBC_OFB \
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(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
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#define XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_CTR_CFB \
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(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_CTR_CFB)
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#define XLR_SEC_VECTOR__CIPHER_AES192__MODE_CTR_CFB \
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(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_MODE_CTR_CFB)
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#define XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_ECB_CBC_OFB \
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(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
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#define XLR_SEC_VECTOR__CIPHER_AES192__MODE_ECB_CBC_OFB \
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(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
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#define XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_CTR_CFB \
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(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_CTR_CFB)
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#define XLR_SEC_VECTOR__CIPHER_AES256__MODE_CTR_CFB \
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(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_MODE_CTR_CFB)
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#define XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_ECB_CBC_OFB \
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(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
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#define XLR_SEC_VECTOR__CIPHER_AES256__MODE_ECB_CBC_OFB \
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(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
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#define XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_F8 \
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(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_F8)
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#define XLR_SEC_VECTOR__CIPHER_AES128__MODE_F8 \
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(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_MODE_F8)
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#define XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_F8 \
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(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_F8)
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#define XLR_SEC_VECTOR__CIPHER_AES192__MODE_F8 \
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(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_MODE_F8)
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#define XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_F8 \
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(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_F8)
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#define XLR_SEC_VECTOR__CIPHER_AES256__MODE_F8 \
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(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_MODE_F8)
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#define XLR_SEC_VECTOR_CIPHER_KASUMI_F8__F9 \
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(XLR_SEC_VECTOR_CIPHER_KASUMI_F8 | XLR_SEC_VECTOR_F9)
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#define XLR_SEC_VECTOR_CIPHER_KASUMI_F8__HMAC \
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(XLR_SEC_VECTOR_CIPHER_KASUMI_F8 | XLR_SEC_VECTOR_HMAC)
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#define XLR_SEC_VECTOR_CIPHER_KASUMI_F8__HMAC2 \
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(XLR_SEC_VECTOR_CIPHER_KASUMI_F8 | XLR_SEC_VECTOR_HMAC2)
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#define XLR_SEC_VECTOR_CIPHER_KASUMI_F8__GCM \
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(XLR_SEC_VECTOR_CIPHER_KASUMI_F8 | XLR_SEC_VECTOR_GCM)
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#define XLR_SEC_VECTOR_CIPHER_ARC4__HMAC2 \
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(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_HMAC2)
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#define XLR_SEC_VECTOR_CIPHER_ARC4__HMAC2__STATE \
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(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_STATE)
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#define XLR_SEC_VECTOR__CIPHER_DES__HMAC2__MODE_ECB_CBC \
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(XLR_SEC_VECTOR_CIPHER_DES | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_ECB_CBC)
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#define XLR_SEC_VECTOR__CIPHER_3DES__HMAC2__MODE_ECB_CBC \
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(XLR_SEC_VECTOR_CIPHER_3DES | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_ECB_CBC)
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#define XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_CTR_CFB \
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(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_CTR_CFB)
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#define XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_ECB_CBC_OFB \
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(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
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#define XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_CTR_CFB \
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(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_CTR_CFB)
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#define XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_ECB_CBC_OFB \
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(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
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#define XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_CTR_CFB \
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(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_CTR_CFB)
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#define XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_ECB_CBC_OFB \
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(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
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#define XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_F8 \
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(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_F8)
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#define XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_F8 \
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(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_F8)
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#define XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_F8 \
|
||||
(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_F8)
|
||||
|
||||
#define XLR_SEC_VECTOR_CIPHER_ARC4__GCM \
|
||||
(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_GCM)
|
||||
|
||||
#define XLR_SEC_VECTOR_CIPHER_ARC4__GCM__STATE \
|
||||
(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_STATE)
|
||||
|
||||
#define XLR_SEC_VECTOR__CIPHER_DES__GCM__MODE_ECB_CBC \
|
||||
(XLR_SEC_VECTOR_CIPHER_DES | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_ECB_CBC)
|
||||
|
||||
#define XLR_SEC_VECTOR__CIPHER_3DES__GCM__MODE_ECB_CBC \
|
||||
(XLR_SEC_VECTOR_CIPHER_3DES | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_ECB_CBC)
|
||||
|
||||
#define XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_CTR_CFB \
|
||||
(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_CTR_CFB)
|
||||
|
||||
#define XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_ECB_CBC_OFB \
|
||||
(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
|
||||
|
||||
#define XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_CTR_CFB \
|
||||
(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_CTR_CFB)
|
||||
|
||||
#define XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_ECB_CBC_OFB \
|
||||
(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
|
||||
|
||||
#define XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_CTR_CFB \
|
||||
(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_CTR_CFB)
|
||||
|
||||
#define XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_ECB_CBC_OFB \
|
||||
(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
|
||||
|
||||
#define XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_F8 \
|
||||
(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_F8)
|
||||
|
||||
#define XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_F8 \
|
||||
(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_F8)
|
||||
|
||||
#define XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_F8 \
|
||||
(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_F8)
|
||||
|
||||
#define XLR_SEC_VECTOR_CIPHER_ARC4__F9 \
|
||||
(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_F9)
|
||||
|
||||
#define XLR_SEC_VECTOR_CIPHER_ARC4__F9__STATE \
|
||||
(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_STATE)
|
||||
|
||||
#define XLR_SEC_VECTOR__CIPHER_DES__F9__MODE_ECB_CBC \
|
||||
(XLR_SEC_VECTOR_CIPHER_DES | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_ECB_CBC)
|
||||
|
||||
#define XLR_SEC_VECTOR__CIPHER_3DES__F9__MODE_ECB_CBC \
|
||||
(XLR_SEC_VECTOR_CIPHER_3DES | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_ECB_CBC)
|
||||
|
||||
#define XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_CTR_CFB \
|
||||
(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_CTR_CFB)
|
||||
|
||||
#define XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_ECB_CBC_OFB \
|
||||
(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
|
||||
|
||||
#define XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_CTR_CFB \
|
||||
(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_CTR_CFB)
|
||||
|
||||
#define XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_ECB_CBC_OFB \
|
||||
(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
|
||||
|
||||
#define XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_CTR_CFB \
|
||||
(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_CTR_CFB)
|
||||
|
||||
#define XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_ECB_CBC_OFB \
|
||||
(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB)
|
||||
|
||||
#define XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_F8 \
|
||||
(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_F8)
|
||||
|
||||
#define XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_F8 \
|
||||
(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_F8)
|
||||
|
||||
#define XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_F8 \
|
||||
(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_F8)
|
||||
|
||||
/*
|
||||
* Cipher Modes
|
||||
*/
|
||||
typedef enum {
|
||||
XLR_SEC_CIPHER_MODE_NONE = 0,
|
||||
XLR_SEC_CIPHER_MODE_PASS = 1,
|
||||
XLR_SEC_CIPHER_MODE_ECB,
|
||||
XLR_SEC_CIPHER_MODE_CBC,
|
||||
XLR_SEC_CIPHER_MODE_OFB,
|
||||
XLR_SEC_CIPHER_MODE_CTR,
|
||||
XLR_SEC_CIPHER_MODE_CFB,
|
||||
XLR_SEC_CIPHER_MODE_F8
|
||||
} XLR_SEC_CIPHER_MODE;
|
||||
|
||||
typedef enum {
|
||||
XLR_SEC_CIPHER_OP_NONE = 0,
|
||||
XLR_SEC_CIPHER_OP_ENCRYPT = 1,
|
||||
XLR_SEC_CIPHER_OP_DECRYPT
|
||||
} XLR_SEC_CIPHER_OP;
|
||||
|
||||
typedef enum {
|
||||
XLR_SEC_CIPHER_TYPE_UNSUPPORTED = -1,
|
||||
XLR_SEC_CIPHER_TYPE_NONE = 0,
|
||||
XLR_SEC_CIPHER_TYPE_DES,
|
||||
XLR_SEC_CIPHER_TYPE_3DES,
|
||||
XLR_SEC_CIPHER_TYPE_AES128,
|
||||
XLR_SEC_CIPHER_TYPE_AES192,
|
||||
XLR_SEC_CIPHER_TYPE_AES256,
|
||||
XLR_SEC_CIPHER_TYPE_ARC4,
|
||||
XLR_SEC_CIPHER_TYPE_KASUMI_F8
|
||||
} XLR_SEC_CIPHER_TYPE;
|
||||
|
||||
typedef enum {
|
||||
XLR_SEC_CIPHER_INIT_OK = 1, /* Preserve old Keys */
|
||||
XLR_SEC_CIPHER_INIT_NK /*Load new Keys */
|
||||
} XLR_SEC_CIPHER_INIT;
|
||||
|
||||
|
||||
/*
|
||||
* Hash Modes
|
||||
*/
|
||||
typedef enum {
|
||||
XLR_SEC_DIGEST_TYPE_UNSUPPORTED = -1,
|
||||
XLR_SEC_DIGEST_TYPE_NONE = 0,
|
||||
XLR_SEC_DIGEST_TYPE_MD5,
|
||||
XLR_SEC_DIGEST_TYPE_SHA1,
|
||||
XLR_SEC_DIGEST_TYPE_SHA256,
|
||||
XLR_SEC_DIGEST_TYPE_SHA384,
|
||||
XLR_SEC_DIGEST_TYPE_SHA512,
|
||||
XLR_SEC_DIGEST_TYPE_GCM,
|
||||
XLR_SEC_DIGEST_TYPE_KASUMI_F9,
|
||||
XLR_SEC_DIGEST_TYPE_HMAC_MD5,
|
||||
XLR_SEC_DIGEST_TYPE_HMAC_SHA1,
|
||||
XLR_SEC_DIGEST_TYPE_HMAC_SHA256,
|
||||
XLR_SEC_DIGEST_TYPE_HMAC_SHA384,
|
||||
XLR_SEC_DIGEST_TYPE_HMAC_SHA512,
|
||||
XLR_SEC_DIGEST_TYPE_HMAC_AES_CBC,
|
||||
XLR_SEC_DIGEST_TYPE_HMAC_AES_XCBC
|
||||
} XLR_SEC_DIGEST_TYPE;
|
||||
|
||||
typedef enum {
|
||||
XLR_SEC_DIGEST_INIT_OLDKEY = 1, /* Preserve old key HMAC key stored in ID registers (moot if HASH.HMAC == 0) */
|
||||
XLR_SEC_DIGEST_INIT_NEWKEY /*Load new HMAC key from memory ctrl section to ID registers */
|
||||
} XLR_SEC_DIGEST_INIT;
|
||||
|
||||
typedef enum {
|
||||
XLR_SEC_DIGEST_SRC_DMA = 1, /* DMA channel */
|
||||
XLR_SEC_DIGEST_SRC_CPHR /*Cipher if word count exceeded Cipher_Offset; else DMA */
|
||||
} XLR_SEC_DIGEST_SRC;
|
||||
|
||||
/*
|
||||
* Checksum Modes
|
||||
*/
|
||||
typedef enum {
|
||||
XLR_SEC_CKSUM_TYPE_NOP = 1,
|
||||
XLR_SEC_CKSUM_TYPE_IP
|
||||
} XLR_SEC_CKSUM_TYPE;
|
||||
|
||||
typedef enum {
|
||||
XLR_SEC_CKSUM_SRC_DMA = 1,
|
||||
XLR_SEC_CKSUM_SRC_CIPHER
|
||||
} XLR_SEC_CKSUM_SRC;
|
||||
|
||||
/*
|
||||
* Packet Modes
|
||||
*/
|
||||
typedef enum {
|
||||
XLR_SEC_LOADHMACKEY_MODE_OLD = 1,
|
||||
XLR_SEC_LOADHMACKEY_MODE_LOAD
|
||||
} XLR_SEC_LOADHMACKEY_MODE;
|
||||
|
||||
typedef enum {
|
||||
XLR_SEC_PADHASH_PADDED = 1,
|
||||
XLR_SEC_PADHASH_PAD
|
||||
} XLR_SEC_PADHASH_MODE;
|
||||
|
||||
typedef enum {
|
||||
XLR_SEC_HASHBYTES_ALL8 = 1,
|
||||
XLR_SEC_HASHBYTES_MSB,
|
||||
XLR_SEC_HASHBYTES_MSW
|
||||
} XLR_SEC_HASHBYTES_MODE;
|
||||
|
||||
typedef enum {
|
||||
XLR_SEC_NEXT_FINISH = 1,
|
||||
XLR_SEC_NEXT_DO
|
||||
} XLR_SEC_NEXT_MODE;
|
||||
|
||||
typedef enum {
|
||||
XLR_SEC_PKT_IV_OLD = 1,
|
||||
XLR_SEC_PKT_IV_NEW
|
||||
} XLR_SEC_PKT_IV_MODE;
|
||||
|
||||
typedef enum {
|
||||
XLR_SEC_LASTWORD_128 = 1,
|
||||
XLR_SEC_LASTWORD_96MASK,
|
||||
XLR_SEC_LASTWORD_64MASK,
|
||||
XLR_SEC_LASTWORD_32MASK
|
||||
} XLR_SEC_LASTWORD_MODE;
|
||||
|
||||
typedef enum {
|
||||
XLR_SEC_CFB_MASK_REGULAR_CTR = 0,
|
||||
XLR_SEC_CFB_MASK_CCMP,
|
||||
XLR_SEC_CFB_MASK_GCM_WITH_SCI,
|
||||
XLR_SEC_CFB_MASK_GCM_WITHOUT_SCI
|
||||
} XLR_SEC_CFB_MASK_MODE;
|
||||
|
||||
/*
|
||||
* Public Key
|
||||
*/
|
||||
typedef enum {
|
||||
RMIPK_BLKWIDTH_512 = 1,
|
||||
RMIPK_BLKWIDTH_1024
|
||||
} RMIPK_BLKWIDTH_MODE;
|
||||
|
||||
typedef enum {
|
||||
RMIPK_LDCONST_OLD = 1,
|
||||
RMIPK_LDCONST_NEW
|
||||
} RMIPK_LDCONST_MODE;
|
||||
|
||||
|
||||
typedef struct xlr_sec_io_s {
|
||||
unsigned int command;
|
||||
unsigned int result_status;
|
||||
unsigned int flags;
|
||||
unsigned int session_num;
|
||||
unsigned int use_callback;
|
||||
unsigned int time_us;
|
||||
unsigned int user_context[2];/*usable for anything by caller*/
|
||||
unsigned int command_context; /* Context (ID) of this command). */
|
||||
unsigned char initial_vector[XLR_SEC_MAX_IV_LENGTH];
|
||||
unsigned char crypt_key[XLR_SEC_MAX_CRYPT_KEY_LENGTH];
|
||||
unsigned char mac_key[XLR_SEC_MAX_AUTH_KEY_LENGTH];
|
||||
|
||||
XLR_SEC_CIPHER_OP cipher_op;
|
||||
XLR_SEC_CIPHER_MODE cipher_mode;
|
||||
XLR_SEC_CIPHER_TYPE cipher_type;
|
||||
XLR_SEC_CIPHER_INIT cipher_init;
|
||||
unsigned int cipher_offset;
|
||||
|
||||
XLR_SEC_DIGEST_TYPE digest_type;
|
||||
XLR_SEC_DIGEST_INIT digest_init;
|
||||
XLR_SEC_DIGEST_SRC digest_src;
|
||||
unsigned int digest_offset;
|
||||
|
||||
XLR_SEC_CKSUM_TYPE cksum_type;
|
||||
XLR_SEC_CKSUM_SRC cksum_src;
|
||||
unsigned int cksum_offset;
|
||||
|
||||
XLR_SEC_LOADHMACKEY_MODE pkt_hmac;
|
||||
XLR_SEC_PADHASH_MODE pkt_hash;
|
||||
XLR_SEC_HASHBYTES_MODE pkt_hashbytes;
|
||||
XLR_SEC_NEXT_MODE pkt_next;
|
||||
XLR_SEC_PKT_IV_MODE pkt_iv;
|
||||
XLR_SEC_LASTWORD_MODE pkt_lastword;
|
||||
|
||||
unsigned int nonce;
|
||||
unsigned int cfb_mask;
|
||||
|
||||
unsigned int iv_offset;
|
||||
unsigned short pad_type;
|
||||
unsigned short rc4_key_len;
|
||||
|
||||
unsigned int num_packets;
|
||||
unsigned int num_fragments;
|
||||
|
||||
uint64_t source_buf;
|
||||
unsigned int source_buf_size;
|
||||
uint64_t dest_buf;
|
||||
unsigned int dest_buf_size;
|
||||
|
||||
uint64_t auth_dest;
|
||||
uint64_t cksum_dest;
|
||||
|
||||
unsigned short rc4_loadstate;
|
||||
unsigned short rc4_savestate;
|
||||
uint64_t rc4_state;
|
||||
|
||||
} xlr_sec_io_t, *xlr_sec_io_pt;
|
||||
|
||||
|
||||
#define XLR_SEC_SESSION(sid) ((sid) & 0x000007ff)
|
||||
#define XLR_SEC_SID(crd,ses) (((crd) << 28) | ((ses) & 0x7ff))
|
||||
|
||||
/*
|
||||
* Length values for cryptography
|
||||
*/
|
||||
/*
|
||||
#define XLR_SEC_DES_KEY_LENGTH 8
|
||||
#define XLR_SEC_3DES_KEY_LENGTH 24
|
||||
#define XLR_SEC_MAX_CRYPT_KEY_LENGTH XLR_SEC_3DES_KEY_LENGTH
|
||||
#define XLR_SEC_IV_LENGTH 8
|
||||
#define XLR_SEC_AES_IV_LENGTH 16
|
||||
#define XLR_SEC_MAX_IV_LENGTH XLR_SEC_AES_IV_LENGTH
|
||||
*/
|
||||
|
||||
#define SEC_MAX_FRAG_LEN 16000
|
||||
|
||||
struct xlr_sec_command {
|
||||
uint16_t session_num;
|
||||
struct cryptop *crp;
|
||||
struct cryptodesc *enccrd, *maccrd;
|
||||
|
||||
xlr_sec_io_t op;
|
||||
};
|
||||
struct xlr_sec_session{
|
||||
uint32_t sessionid;
|
||||
int hs_used;
|
||||
int hs_mlen;
|
||||
struct xlr_sec_command cmd;
|
||||
void* desc_ptr;
|
||||
uint8_t multi_frag_flag;
|
||||
};
|
||||
|
||||
/*
|
||||
* Holds data specific to rmi security accelerators
|
||||
*/
|
||||
struct xlr_sec_softc {
|
||||
device_t sc_dev; /* device backpointer */
|
||||
struct mtx sc_mtx; /* per-instance lock */
|
||||
|
||||
int32_t sc_cid;
|
||||
struct xlr_sec_session *sc_sessions;
|
||||
int sc_nsessions;
|
||||
xlr_reg_t* mmio;
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
|
||||
union xlr_sec_operand_t {
|
||||
struct mbuf *m;
|
||||
struct uio *io;
|
||||
void *buf;
|
||||
}xlr_sec_operand;
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* this is passed to packet setup to optimize */
|
||||
#define XLR_SEC_SETUP_OP_CIPHER 0x00000001
|
||||
#define XLR_SEC_SETUP_OP_HMAC 0x00000002
|
||||
#define XLR_SEC_SETUP_OP_CIPHER_HMAC (XLR_SEC_SETUP_OP_CIPHER | XLR_SEC_SETUP_OP_HMAC)
|
||||
/* this is passed to control_setup to update w/preserving existing keys */
|
||||
#define XLR_SEC_SETUP_OP_PRESERVE_HMAC_KEY 0x80000000
|
||||
#define XLR_SEC_SETUP_OP_PRESERVE_CIPHER_KEY 0x40000000
|
||||
#define XLR_SEC_SETUP_OP_UPDATE_KEYS 0x00000010
|
||||
#define XLR_SEC_SETUP_OP_FLIP_3DES_KEY 0x00000020
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Message Ring Specifics
|
||||
*/
|
||||
|
||||
#define SEC_MSGRING_WORDSIZE 2
|
||||
|
||||
|
||||
/*
|
||||
*
|
||||
*
|
||||
* rwR 31 30 29 27 26 24 23 21 20 18
|
||||
* | NA | RSA0Out | Rsa0In | Pipe3Out | Pipe3In | ...
|
||||
*
|
||||
* 17 15 14 12 11 9 8 6 5 3 2 0
|
||||
* | Pipe2Out | Pipe2In | Pipe1In | Pipe1In | Pipe0Out | Pipe0In |
|
||||
*
|
||||
* DMA CREDIT REG -
|
||||
* NUMBER OF CREDITS PER PIPE
|
||||
*/
|
||||
|
||||
#define SEC_DMA_CREDIT_RSA0_OUT_FOUR 0x20000000
|
||||
#define SEC_DMA_CREDIT_RSA0_OUT_TWO 0x10000000
|
||||
#define SEC_DMA_CREDIT_RSA0_OUT_ONE 0x08000000
|
||||
|
||||
#define SEC_DMA_CREDIT_RSA0_IN_FOUR 0x04000000
|
||||
#define SEC_DMA_CREDIT_RSA0_IN_TWO 0x02000000
|
||||
#define SEC_DMA_CREDIT_RSA0_IN_ONE 0x01000000
|
||||
|
||||
#define SEC_DMA_CREDIT_PIPE3_OUT_FOUR 0x00800000
|
||||
#define SEC_DMA_CREDIT_PIPE3_OUT_TWO 0x00400000
|
||||
#define SEC_DMA_CREDIT_PIPE3_OUT_ONE 0x00200000
|
||||
|
||||
#define SEC_DMA_CREDIT_PIPE3_IN_FOUR 0x00100000
|
||||
#define SEC_DMA_CREDIT_PIPE3_IN_TWO 0x00080000
|
||||
#define SEC_DMA_CREDIT_PIPE3_IN_ONE 0x00040000
|
||||
|
||||
#define SEC_DMA_CREDIT_PIPE2_OUT_FOUR 0x00020000
|
||||
#define SEC_DMA_CREDIT_PIPE2_OUT_TWO 0x00010000
|
||||
#define SEC_DMA_CREDIT_PIPE2_OUT_ONE 0x00008000
|
||||
|
||||
#define SEC_DMA_CREDIT_PIPE2_IN_FOUR 0x00004000
|
||||
#define SEC_DMA_CREDIT_PIPE2_IN_TWO 0x00002000
|
||||
#define SEC_DMA_CREDIT_PIPE2_IN_ONE 0x00001000
|
||||
|
||||
#define SEC_DMA_CREDIT_PIPE1_OUT_FOUR 0x00000800
|
||||
#define SEC_DMA_CREDIT_PIPE1_OUT_TWO 0x00000400
|
||||
#define SEC_DMA_CREDIT_PIPE1_OUT_ONE 0x00000200
|
||||
|
||||
#define SEC_DMA_CREDIT_PIPE1_IN_FOUR 0x00000100
|
||||
#define SEC_DMA_CREDIT_PIPE1_IN_TWO 0x00000080
|
||||
#define SEC_DMA_CREDIT_PIPE1_IN_ONE 0x00000040
|
||||
|
||||
#define SEC_DMA_CREDIT_PIPE0_OUT_FOUR 0x00000020
|
||||
#define SEC_DMA_CREDIT_PIPE0_OUT_TWO 0x00000010
|
||||
#define SEC_DMA_CREDIT_PIPE0_OUT_ONE 0x00000008
|
||||
|
||||
#define SEC_DMA_CREDIT_PIPE0_IN_FOUR 0x00000004
|
||||
#define SEC_DMA_CREDIT_PIPE0_IN_TWO 0x00000002
|
||||
#define SEC_DMA_CREDIT_PIPE0_IN_ONE 0x00000001
|
||||
|
||||
|
||||
/*
|
||||
* Currently, FOUR credits per PIPE
|
||||
* 0x24924924
|
||||
*/
|
||||
#define SEC_DMA_CREDIT_CONFIG SEC_DMA_CREDIT_RSA0_OUT_FOUR | \
|
||||
SEC_DMA_CREDIT_RSA0_IN_FOUR | \
|
||||
SEC_DMA_CREDIT_PIPE3_OUT_FOUR | \
|
||||
SEC_DMA_CREDIT_PIPE3_IN_FOUR | \
|
||||
SEC_DMA_CREDIT_PIPE2_OUT_FOUR | \
|
||||
SEC_DMA_CREDIT_PIPE2_IN_FOUR | \
|
||||
SEC_DMA_CREDIT_PIPE1_OUT_FOUR | \
|
||||
SEC_DMA_CREDIT_PIPE1_IN_FOUR | \
|
||||
SEC_DMA_CREDIT_PIPE0_OUT_FOUR | \
|
||||
SEC_DMA_CREDIT_PIPE0_IN_FOUR
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* CONFIG2
|
||||
* 31 5 4 3
|
||||
* | NA | PIPE3_DEF_DBL_ISS | PIPE2_DEF_DBL_ISS | ...
|
||||
*
|
||||
* 2 1 0
|
||||
* ... | PIPE1_DEF_DBL_ISS | PIPE0_DEF_DBL_ISS | ROUND_ROBIN_MODE |
|
||||
*
|
||||
* DBL_ISS - mode for SECENG and DMA controller which slows down transfers
|
||||
* (to be conservativei; 0=Disable,1=Enable).
|
||||
* ROUND_ROBIN - mode where SECENG dispatches operations to PIPE0-PIPE3
|
||||
* and all messages are sent to PIPE0.
|
||||
*
|
||||
*/
|
||||
|
||||
#define SEC_CFG2_PIPE3_DBL_ISS_ON 0x00000010
|
||||
#define SEC_CFG2_PIPE3_DBL_ISS_OFF 0x00000000
|
||||
#define SEC_CFG2_PIPE2_DBL_ISS_ON 0x00000008
|
||||
#define SEC_CFG2_PIPE2_DBL_ISS_OFF 0x00000000
|
||||
#define SEC_CFG2_PIPE1_DBL_ISS_ON 0x00000004
|
||||
#define SEC_CFG2_PIPE1_DBL_ISS_OFF 0x00000000
|
||||
#define SEC_CFG2_PIPE0_DBL_ISS_ON 0x00000002
|
||||
#define SEC_CFG2_PIPE0_DBL_ISS_OFF 0x00000000
|
||||
#define SEC_CFG2_ROUND_ROBIN_ON 0x00000001
|
||||
#define SEC_CFG2_ROUND_ROBIN_OFF 0x00000000
|
||||
|
||||
|
||||
enum sec_pipe_config {
|
||||
|
||||
SEC_PIPE_CIPHER_KEY0_L0 = 0x00,
|
||||
SEC_PIPE_CIPHER_KEY0_HI,
|
||||
SEC_PIPE_CIPHER_KEY1_LO,
|
||||
SEC_PIPE_CIPHER_KEY1_HI,
|
||||
SEC_PIPE_CIPHER_KEY2_LO,
|
||||
SEC_PIPE_CIPHER_KEY2_HI,
|
||||
SEC_PIPE_CIPHER_KEY3_LO,
|
||||
SEC_PIPE_CIPHER_KEY3_HI,
|
||||
SEC_PIPE_HMAC_KEY0_LO,
|
||||
SEC_PIPE_HMAC_KEY0_HI,
|
||||
SEC_PIPE_HMAC_KEY1_LO,
|
||||
SEC_PIPE_HMAC_KEY1_HI,
|
||||
SEC_PIPE_HMAC_KEY2_LO,
|
||||
SEC_PIPE_HMAC_KEY2_HI,
|
||||
SEC_PIPE_HMAC_KEY3_LO,
|
||||
SEC_PIPE_HMAC_KEY3_HI,
|
||||
SEC_PIPE_HMAC_KEY4_LO,
|
||||
SEC_PIPE_HMAC_KEY4_HI,
|
||||
SEC_PIPE_HMAC_KEY5_LO,
|
||||
SEC_PIPE_HMAC_KEY5_HI,
|
||||
SEC_PIPE_HMAC_KEY6_LO,
|
||||
SEC_PIPE_HMAC_KEY6_HI,
|
||||
SEC_PIPE_HMAC_KEY7_LO,
|
||||
SEC_PIPE_HMAC_KEY7_HI,
|
||||
SEC_PIPE_NCFBM_LO,
|
||||
SEC_PIPE_NCFBM_HI,
|
||||
SEC_PIPE_INSTR_LO,
|
||||
SEC_PIPE_INSTR_HI,
|
||||
SEC_PIPE_RSVD0,
|
||||
SEC_PIPE_RSVD1,
|
||||
SEC_PIPE_RSVD2,
|
||||
SEC_PIPE_RSVD3,
|
||||
|
||||
SEC_PIPE_DF_PTRS0,
|
||||
SEC_PIPE_DF_PTRS1,
|
||||
SEC_PIPE_DF_PTRS2,
|
||||
SEC_PIPE_DF_PTRS3,
|
||||
SEC_PIPE_DF_PTRS4,
|
||||
SEC_PIPE_DF_PTRS5,
|
||||
SEC_PIPE_DF_PTRS6,
|
||||
SEC_PIPE_DF_PTRS7,
|
||||
|
||||
SEC_PIPE_DU_DATA_IN_LO,
|
||||
SEC_PIPE_DU_DATA_IN_HI,
|
||||
SEC_PIPE_DU_DATA_IN_CTRL,
|
||||
SEC_PIPE_DU_DATA_OUT_LO,
|
||||
SEC_PIPE_DU_DATA_OUT_HI,
|
||||
SEC_PIPE_DU_DATA_OUT_CTRL,
|
||||
|
||||
SEC_PIPE_STATE0,
|
||||
SEC_PIPE_STATE1,
|
||||
SEC_PIPE_STATE2,
|
||||
SEC_PIPE_STATE3,
|
||||
SEC_PIPE_STATE4,
|
||||
SEC_PIPE_INCLUDE_MASK0,
|
||||
SEC_PIPE_INCLUDE_MASK1,
|
||||
SEC_PIPE_INCLUDE_MASK2,
|
||||
SEC_PIPE_INCLUDE_MASK3,
|
||||
SEC_PIPE_INCLUDE_MASK4,
|
||||
SEC_PIPE_EXCLUDE_MASK0,
|
||||
SEC_PIPE_EXCLUDE_MASK1,
|
||||
SEC_PIPE_EXCLUDE_MASK2,
|
||||
SEC_PIPE_EXCLUDE_MASK3,
|
||||
SEC_PIPE_EXCLUDE_MASK4,
|
||||
};
|
||||
|
||||
|
||||
enum sec_pipe_base_config {
|
||||
|
||||
SEC_PIPE0_BASE = 0x00,
|
||||
SEC_PIPE1_BASE = 0x40,
|
||||
SEC_PIPE2_BASE = 0x80,
|
||||
SEC_PIPE3_BASE = 0xc0
|
||||
|
||||
};
|
||||
|
||||
enum sec_rsa_config {
|
||||
|
||||
SEC_RSA_PIPE0_DU_DATA_IN_LO = 0x100,
|
||||
SEC_RSA_PIPE0_DU_DATA_IN_HI,
|
||||
SEC_RSA_PIPE0_DU_DATA_IN_CTRL,
|
||||
SEC_RSA_PIPE0_DU_DATA_OUT_LO,
|
||||
SEC_RSA_PIPE0_DU_DATA_OUT_HI,
|
||||
SEC_RSA_PIPE0_DU_DATA_OUT_CTRL,
|
||||
SEC_RSA_RSVD0,
|
||||
SEC_RSA_RSVD1,
|
||||
|
||||
SEC_RSA_PIPE0_STATE0,
|
||||
SEC_RSA_PIPE0_STATE1,
|
||||
SEC_RSA_PIPE0_STATE2,
|
||||
SEC_RSA_PIPE0_INCLUDE_MASK0,
|
||||
SEC_RSA_PIPE0_INCLUDE_MASK1,
|
||||
SEC_RSA_PIPE0_INCLUDE_MASK2,
|
||||
SEC_RSA_PIPE0_EXCLUDE_MASK0,
|
||||
SEC_RSA_PIPE0_EXCLUDE_MASK1,
|
||||
SEC_RSA_PIPE0_EXCLUDE_MASK2,
|
||||
SEC_RSA_PIPE0_EVENT_CTR
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
enum sec_config {
|
||||
|
||||
SEC_DMA_CREDIT = 0x140,
|
||||
SEC_CONFIG1,
|
||||
SEC_CONFIG2,
|
||||
SEC_CONFIG3,
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
enum sec_debug_config {
|
||||
|
||||
SEC_DW0_DESCRIPTOR0_LO = 0x180,
|
||||
SEC_DW0_DESCRIPTOR0_HI,
|
||||
SEC_DW0_DESCRIPTOR1_LO,
|
||||
SEC_DW0_DESCRIPTOR1_HI,
|
||||
SEC_DW1_DESCRIPTOR0_LO,
|
||||
SEC_DW1_DESCRIPTOR0_HI,
|
||||
SEC_DW1_DESCRIPTOR1_LO,
|
||||
SEC_DW1_DESCRIPTOR1_HI,
|
||||
SEC_DW2_DESCRIPTOR0_LO,
|
||||
SEC_DW2_DESCRIPTOR0_HI,
|
||||
SEC_DW2_DESCRIPTOR1_LO,
|
||||
SEC_DW2_DESCRIPTOR1_HI,
|
||||
SEC_DW3_DESCRIPTOR0_LO,
|
||||
SEC_DW3_DESCRIPTOR0_HI,
|
||||
SEC_DW3_DESCRIPTOR1_LO,
|
||||
SEC_DW3_DESCRIPTOR1_HI,
|
||||
|
||||
SEC_STATE0,
|
||||
SEC_STATE1,
|
||||
SEC_STATE2,
|
||||
SEC_INCLUDE_MASK0,
|
||||
SEC_INCLUDE_MASK1,
|
||||
SEC_INCLUDE_MASK2,
|
||||
SEC_EXCLUDE_MASK0,
|
||||
SEC_EXCLUDE_MASK1,
|
||||
SEC_EXCLUDE_MASK2,
|
||||
SEC_EVENT_CTR
|
||||
|
||||
};
|
||||
|
||||
|
||||
enum sec_msgring_bucket_config {
|
||||
|
||||
SEC_BIU_CREDITS = 0x308,
|
||||
|
||||
SEC_MSG_BUCKET0_SIZE = 0x320,
|
||||
SEC_MSG_BUCKET1_SIZE,
|
||||
SEC_MSG_BUCKET2_SIZE,
|
||||
SEC_MSG_BUCKET3_SIZE,
|
||||
SEC_MSG_BUCKET4_SIZE,
|
||||
SEC_MSG_BUCKET5_SIZE,
|
||||
SEC_MSG_BUCKET6_SIZE,
|
||||
SEC_MSG_BUCKET7_SIZE,
|
||||
};
|
||||
|
||||
enum sec_msgring_credit_config {
|
||||
|
||||
SEC_CC_CPU0_0 = 0x380,
|
||||
SEC_CC_CPU1_0 = 0x388,
|
||||
SEC_CC_CPU2_0 = 0x390,
|
||||
SEC_CC_CPU3_0 = 0x398,
|
||||
SEC_CC_CPU4_0 = 0x3a0,
|
||||
SEC_CC_CPU5_0 = 0x3a8,
|
||||
SEC_CC_CPU6_0 = 0x3b0,
|
||||
SEC_CC_CPU7_0 = 0x3b8
|
||||
|
||||
};
|
||||
|
||||
enum sec_engine_id {
|
||||
SEC_PIPE0,
|
||||
SEC_PIPE1,
|
||||
SEC_PIPE2,
|
||||
SEC_PIPE3,
|
||||
SEC_RSA
|
||||
};
|
||||
|
||||
enum sec_cipher {
|
||||
SEC_AES256_MODE_HMAC,
|
||||
SEC_AES256_MODE,
|
||||
SEC_AES256_HMAC,
|
||||
SEC_AES256,
|
||||
SEC_AES192_MODE_HMAC,
|
||||
SEC_AES192_MODE,
|
||||
SEC_AES192_HMAC,
|
||||
SEC_AES192,
|
||||
SEC_AES128_MODE_HMAC,
|
||||
SEC_AES128_MODE,
|
||||
SEC_AES128_HMAC,
|
||||
SEC_AES128,
|
||||
SEC_DES_HMAC,
|
||||
SEC_DES,
|
||||
SEC_3DES,
|
||||
SEC_3DES_HMAC,
|
||||
SEC_HMAC
|
||||
};
|
||||
|
||||
enum sec_msgrng_msg_ctrl_config {
|
||||
SEC_EOP=5,
|
||||
SEC_SOP=6,
|
||||
};
|
||||
|
||||
|
||||
|
||||
void xlr_sec_init( struct xlr_sec_softc *sc) ;
|
||||
|
||||
int xlr_sec_setup(struct xlr_sec_session* ses,
|
||||
struct xlr_sec_command *cmd, symkey_desc_pt desc);
|
||||
|
||||
symkey_desc_pt xlr_sec_allocate_desc(void*);
|
||||
|
||||
#endif
|
||||
617
sys/dev/rmi/sec/rmisec.c
Normal file
617
sys/dev/rmi/sec/rmisec.c
Normal file
|
|
@ -0,0 +1,617 @@
|
|||
/*-
|
||||
* Copyright (c) 2003-2009 RMI Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of RMI Corporation, nor the names of its contributors,
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* RMI_BSD */
|
||||
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/proc.h>
|
||||
#include <sys/errno.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/module.h>
|
||||
#include <sys/mbuf.h>
|
||||
#include <sys/lock.h>
|
||||
#include <sys/mutex.h>
|
||||
#include <sys/sysctl.h>
|
||||
|
||||
#include <vm/vm.h>
|
||||
#include <vm/pmap.h>
|
||||
|
||||
#include <machine/bus.h>
|
||||
#include <machine/resource.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/rman.h>
|
||||
|
||||
#include <opencrypto/cryptodev.h>
|
||||
#include <sys/random.h>
|
||||
|
||||
#include <dev/rmi/sec/rmilib.h>
|
||||
|
||||
/*#define RMI_SEC_DEBUG */
|
||||
|
||||
|
||||
void xlr_sec_print_data(struct cryptop *crp);
|
||||
|
||||
static int xlr_sec_newsession(void *arg, uint32_t *sidp, struct cryptoini *cri);
|
||||
static int xlr_sec_freesession(void *arg, uint64_t tid);
|
||||
static int xlr_sec_process(void *arg, struct cryptop *crp, int hint);
|
||||
|
||||
|
||||
static int xlr_sec_probe(device_t);
|
||||
static int xlr_sec_attach(device_t);
|
||||
static int xlr_sec_detach(device_t);
|
||||
|
||||
|
||||
static device_method_t xlr_sec_methods[] = {
|
||||
/* device interface */
|
||||
DEVMETHOD(device_probe, xlr_sec_probe),
|
||||
DEVMETHOD(device_attach, xlr_sec_attach),
|
||||
DEVMETHOD(device_detach, xlr_sec_detach),
|
||||
|
||||
/* bus interface */
|
||||
DEVMETHOD(bus_print_child, bus_generic_print_child),
|
||||
DEVMETHOD(bus_driver_added, bus_generic_driver_added),
|
||||
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static driver_t xlr_sec_driver = {
|
||||
"rmisec",
|
||||
xlr_sec_methods,
|
||||
sizeof (struct xlr_sec_softc)
|
||||
};
|
||||
static devclass_t xlr_sec_devclass;
|
||||
|
||||
DRIVER_MODULE(rmisec, iodi, xlr_sec_driver, xlr_sec_devclass, 0, 0);
|
||||
MODULE_DEPEND(rmisec, crypto, 1, 1, 1);
|
||||
|
||||
|
||||
|
||||
static int
|
||||
xlr_sec_probe(device_t dev)
|
||||
{
|
||||
return (BUS_PROBE_DEFAULT);
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Attach an interface that successfully probed.
|
||||
*/
|
||||
static int
|
||||
xlr_sec_attach(device_t dev)
|
||||
{
|
||||
|
||||
struct xlr_sec_softc *sc = device_get_softc(dev);
|
||||
|
||||
bzero(sc, sizeof (*sc));
|
||||
sc->sc_dev = dev;
|
||||
|
||||
|
||||
mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "rmi crypto driver", MTX_DEF);
|
||||
|
||||
sc->sc_cid = crypto_get_driverid(0);
|
||||
if (sc->sc_cid < 0) {
|
||||
printf("xlr_sec - error : could not get the driver id\n");
|
||||
goto error_exit;
|
||||
}
|
||||
|
||||
|
||||
if(crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0,
|
||||
xlr_sec_newsession, xlr_sec_freesession, xlr_sec_process, sc)!=0)
|
||||
printf("register failed for CRYPTO_DES_CBC\n");
|
||||
|
||||
if(crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0,
|
||||
xlr_sec_newsession, xlr_sec_freesession, xlr_sec_process, sc)!=0)
|
||||
printf("register failed for CRYPTO_3DES_CBC\n");
|
||||
|
||||
if(crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0,
|
||||
xlr_sec_newsession, xlr_sec_freesession,
|
||||
xlr_sec_process, sc)!=0)
|
||||
printf("register failed for CRYPTO_AES_CBC\n");
|
||||
|
||||
if(crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0,
|
||||
xlr_sec_newsession, xlr_sec_freesession, xlr_sec_process, sc)!=0)
|
||||
printf("register failed for CRYPTO_ARC4\n");
|
||||
|
||||
|
||||
if(crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0,
|
||||
xlr_sec_newsession, xlr_sec_freesession, xlr_sec_process, sc)!=0)
|
||||
printf("register failed for CRYPTO_MD5\n");
|
||||
|
||||
if(crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0,
|
||||
xlr_sec_newsession, xlr_sec_freesession, xlr_sec_process, sc)!=0)
|
||||
printf("register failed for CRYPTO_SHA1\n");
|
||||
|
||||
if(crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0,
|
||||
xlr_sec_newsession, xlr_sec_freesession, xlr_sec_process, sc)!=0)
|
||||
printf("register failed for CRYPTO_MD5_HMAC\n");
|
||||
|
||||
if(crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0,
|
||||
xlr_sec_newsession, xlr_sec_freesession, xlr_sec_process, sc)!=0)
|
||||
printf("register failed for CRYPTO_SHA1_HMAC\n");
|
||||
|
||||
|
||||
xlr_sec_init(sc);
|
||||
return (0);
|
||||
|
||||
|
||||
error_exit:
|
||||
return (ENXIO);
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Detach an interface that successfully probed.
|
||||
*/
|
||||
static int
|
||||
xlr_sec_detach(device_t dev)
|
||||
{
|
||||
int sesn;
|
||||
struct xlr_sec_softc *sc = device_get_softc(dev);
|
||||
struct xlr_sec_session *ses = NULL;
|
||||
symkey_desc_pt desc ;
|
||||
|
||||
for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
|
||||
ses = &sc->sc_sessions[sesn];
|
||||
desc = (symkey_desc_pt)ses->desc_ptr;
|
||||
free(desc->user.kern_src, M_DEVBUF);
|
||||
free(desc->user.kern_dest, M_DEVBUF);
|
||||
free(desc->next_src_buf, M_DEVBUF);
|
||||
free(desc->next_dest_buf, M_DEVBUF);
|
||||
free(ses->desc_ptr, M_DEVBUF) ;
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* Allocate a new 'session' and return an encoded session id. 'sidp'
|
||||
* contains our registration id, and should contain an encoded session
|
||||
* id on successful allocation.
|
||||
*/
|
||||
static int
|
||||
xlr_sec_newsession(void *arg, u_int32_t *sidp, struct cryptoini *cri)
|
||||
{
|
||||
struct cryptoini *c;
|
||||
struct xlr_sec_softc *sc = arg;
|
||||
int mac = 0, cry = 0, sesn;
|
||||
struct xlr_sec_session *ses = NULL;
|
||||
|
||||
|
||||
if (sidp == NULL || cri == NULL || sc == NULL)
|
||||
return (EINVAL);
|
||||
|
||||
|
||||
if (sc->sc_sessions == NULL) {
|
||||
ses = sc->sc_sessions = (struct xlr_sec_session *)malloc(
|
||||
sizeof(struct xlr_sec_session), M_DEVBUF, M_NOWAIT);
|
||||
if (ses == NULL)
|
||||
return (ENOMEM);
|
||||
|
||||
ses->desc_ptr = (void*) xlr_sec_allocate_desc((void*)ses);
|
||||
if(ses->desc_ptr == NULL)
|
||||
return (ENOMEM);
|
||||
|
||||
sesn = 0;
|
||||
ses->sessionid = sesn;
|
||||
sc->sc_nsessions = 1;
|
||||
} else {
|
||||
for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
|
||||
if (!sc->sc_sessions[sesn].hs_used) {
|
||||
ses = &sc->sc_sessions[sesn];
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (ses == NULL) {
|
||||
sesn = sc->sc_nsessions;
|
||||
ses = (struct xlr_sec_session *)malloc((sesn + 1) *
|
||||
sizeof(struct xlr_sec_session), M_DEVBUF, M_NOWAIT);
|
||||
if (ses == NULL)
|
||||
return (ENOMEM);
|
||||
bcopy(sc->sc_sessions, ses, sesn * sizeof(struct xlr_sec_session));
|
||||
bzero(sc->sc_sessions, sesn * sizeof(struct xlr_sec_session));
|
||||
free(sc->sc_sessions, M_DEVBUF);
|
||||
sc->sc_sessions = ses;
|
||||
ses = &sc->sc_sessions[sesn];
|
||||
ses->sessionid = sesn;
|
||||
ses->desc_ptr = (void*) xlr_sec_allocate_desc((void*)ses);
|
||||
if(ses->desc_ptr == NULL)
|
||||
return (ENOMEM);
|
||||
sc->sc_nsessions++;
|
||||
}
|
||||
}
|
||||
ses->hs_used = 1;
|
||||
|
||||
|
||||
for (c = cri; c != NULL; c = c->cri_next) {
|
||||
|
||||
switch (c->cri_alg) {
|
||||
case CRYPTO_MD5:
|
||||
case CRYPTO_SHA1:
|
||||
case CRYPTO_MD5_HMAC:
|
||||
case CRYPTO_SHA1_HMAC:
|
||||
if (mac)
|
||||
return (EINVAL);
|
||||
mac = 1;
|
||||
ses->hs_mlen = c->cri_mlen;
|
||||
if (ses->hs_mlen == 0) {
|
||||
switch (c->cri_alg) {
|
||||
case CRYPTO_MD5:
|
||||
case CRYPTO_MD5_HMAC:
|
||||
ses->hs_mlen = 16;
|
||||
break;
|
||||
case CRYPTO_SHA1:
|
||||
case CRYPTO_SHA1_HMAC:
|
||||
ses->hs_mlen = 20;
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
case CRYPTO_DES_CBC:
|
||||
case CRYPTO_3DES_CBC:
|
||||
case CRYPTO_AES_CBC:
|
||||
/* XXX this may read fewer, does it matter? */
|
||||
/* read_random(ses->hs_iv,
|
||||
c->cri_alg == CRYPTO_AES_CBC ?
|
||||
XLR_SEC_AES_IV_LENGTH : XLR_SEC_IV_LENGTH);
|
||||
*/
|
||||
/*FALLTHROUGH*/
|
||||
case CRYPTO_ARC4:
|
||||
if (cry)
|
||||
return (EINVAL);
|
||||
cry = 1;
|
||||
break;
|
||||
default:
|
||||
return (EINVAL);
|
||||
}
|
||||
}
|
||||
if (mac == 0 && cry == 0)
|
||||
return (EINVAL);
|
||||
|
||||
*sidp = XLR_SEC_SID(device_get_unit(sc->sc_dev), sesn);
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Deallocate a session.
|
||||
* XXX this routine should run a zero'd mac/encrypt key into context ram.
|
||||
* XXX to blow away any keys already stored there.
|
||||
*/
|
||||
static int
|
||||
xlr_sec_freesession(void *arg, u_int64_t tid)
|
||||
{
|
||||
struct xlr_sec_softc *sc = arg;
|
||||
int session;
|
||||
u_int32_t sid = CRYPTO_SESID2LID(tid);
|
||||
|
||||
if (sc == NULL)
|
||||
return (EINVAL);
|
||||
|
||||
session = XLR_SEC_SESSION(sid);
|
||||
if (session >= sc->sc_nsessions)
|
||||
return (EINVAL);
|
||||
|
||||
sc->sc_sessions[session].hs_used = 0;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
#ifdef RMI_SEC_DEBUG
|
||||
|
||||
void xlr_sec_print_data(struct cryptop *crp)
|
||||
{
|
||||
int i, key_len;
|
||||
struct cryptodesc *crp_desc;
|
||||
|
||||
printf("session id = 0x%llx, crp_ilen = %d, crp_olen=%d \n",
|
||||
crp->crp_sid, crp->crp_ilen, crp->crp_olen);
|
||||
|
||||
printf("crp_flags = 0x%x\n", crp->crp_flags);
|
||||
|
||||
|
||||
printf("crp buf:\n");
|
||||
for(i=0; i<crp->crp_ilen; i++)
|
||||
{
|
||||
printf("%c ",crp->crp_buf[i] );
|
||||
if(i%10 == 0) printf("\n");
|
||||
}
|
||||
|
||||
printf("\n");
|
||||
printf("****************** desc ****************\n");
|
||||
crp_desc = crp->crp_desc;
|
||||
printf("crd_skip=%d, crd_len=%d, crd_flags=0x%x, crd_alg=%d\n",
|
||||
crp_desc->crd_skip, crp_desc->crd_len, crp_desc->crd_flags, crp_desc->crd_alg);
|
||||
|
||||
key_len = crp_desc->crd_klen / 8;
|
||||
printf("key(%d) :\n",key_len);
|
||||
for(i=0; i< key_len; i++)
|
||||
printf("%d", crp_desc->crd_key[i]);
|
||||
printf("\n");
|
||||
|
||||
printf(" IV : \n");
|
||||
for(i=0; i< EALG_MAX_BLOCK_LEN; i++)
|
||||
printf("%d", crp_desc->crd_iv[i]);
|
||||
printf("\n");
|
||||
|
||||
printf("crd_next=%p\n", crp_desc->crd_next);
|
||||
return;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
static int
|
||||
xlr_sec_process(void *arg, struct cryptop *crp, int hint)
|
||||
{
|
||||
struct xlr_sec_softc *sc = arg;
|
||||
struct xlr_sec_command *cmd = NULL;
|
||||
int session, err;
|
||||
struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
|
||||
struct xlr_sec_session* ses;
|
||||
|
||||
if (crp == NULL || crp->crp_callback == NULL) {
|
||||
return (EINVAL);
|
||||
}
|
||||
|
||||
session = XLR_SEC_SESSION(crp->crp_sid);
|
||||
if (sc == NULL || session >= sc->sc_nsessions) {
|
||||
err = EINVAL;
|
||||
goto errout;
|
||||
}
|
||||
|
||||
ses = &sc->sc_sessions[session];
|
||||
|
||||
cmd = &ses->cmd ;
|
||||
if (cmd == NULL) {
|
||||
err = ENOMEM;
|
||||
goto errout;
|
||||
}
|
||||
|
||||
|
||||
crd1 = crp->crp_desc;
|
||||
if (crd1 == NULL) {
|
||||
err = EINVAL;
|
||||
goto errout;
|
||||
}
|
||||
|
||||
crd2 = crd1->crd_next;
|
||||
|
||||
if (crd2 == NULL) {
|
||||
if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
|
||||
crd1->crd_alg == CRYPTO_SHA1_HMAC ||
|
||||
crd1->crd_alg == CRYPTO_SHA1 ||
|
||||
crd1->crd_alg == CRYPTO_MD5) {
|
||||
maccrd = crd1;
|
||||
enccrd = NULL;
|
||||
} else if (crd1->crd_alg == CRYPTO_DES_CBC ||
|
||||
crd1->crd_alg == CRYPTO_3DES_CBC ||
|
||||
crd1->crd_alg == CRYPTO_AES_CBC ||
|
||||
crd1->crd_alg == CRYPTO_ARC4) {
|
||||
maccrd = NULL;
|
||||
enccrd = crd1;
|
||||
} else {
|
||||
err = EINVAL;
|
||||
goto errout;
|
||||
}
|
||||
} else {
|
||||
if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
|
||||
crd1->crd_alg == CRYPTO_SHA1_HMAC ||
|
||||
crd1->crd_alg == CRYPTO_MD5 ||
|
||||
crd1->crd_alg == CRYPTO_SHA1) &&
|
||||
(crd2->crd_alg == CRYPTO_DES_CBC ||
|
||||
crd2->crd_alg == CRYPTO_3DES_CBC ||
|
||||
crd2->crd_alg == CRYPTO_AES_CBC ||
|
||||
crd2->crd_alg == CRYPTO_ARC4)){
|
||||
maccrd = crd1;
|
||||
enccrd = crd2;
|
||||
} else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
|
||||
crd1->crd_alg == CRYPTO_ARC4 ||
|
||||
crd1->crd_alg == CRYPTO_3DES_CBC ||
|
||||
crd1->crd_alg == CRYPTO_AES_CBC) &&
|
||||
(crd2->crd_alg == CRYPTO_MD5_HMAC ||
|
||||
crd2->crd_alg == CRYPTO_SHA1_HMAC ||
|
||||
crd2->crd_alg == CRYPTO_MD5 ||
|
||||
crd2->crd_alg == CRYPTO_SHA1) &&
|
||||
(crd1->crd_flags & CRD_F_ENCRYPT)) {
|
||||
enccrd = crd1;
|
||||
maccrd = crd2;
|
||||
} else {
|
||||
err = EINVAL;
|
||||
goto errout;
|
||||
}
|
||||
}
|
||||
|
||||
bzero(&cmd->op, sizeof(xlr_sec_io_t));
|
||||
|
||||
cmd->op.source_buf = (uint64_t)(unsigned long) crp->crp_buf;
|
||||
cmd->op.source_buf_size = crp->crp_ilen;
|
||||
if(crp->crp_flags & CRYPTO_F_REL){
|
||||
cmd->op.dest_buf = (uint64_t)(unsigned long)crp->crp_buf;
|
||||
cmd->op.dest_buf_size = crp->crp_ilen ;
|
||||
}
|
||||
else{
|
||||
cmd->op.dest_buf = (uint64_t)(unsigned long)crp->crp_buf;
|
||||
cmd->op.dest_buf_size = crp->crp_ilen ;
|
||||
}
|
||||
cmd->op.num_packets = 1;
|
||||
cmd->op.num_fragments = 1;
|
||||
|
||||
|
||||
if(cmd->op.source_buf_size > SEC_MAX_FRAG_LEN){
|
||||
ses->multi_frag_flag = 1;
|
||||
}
|
||||
else{
|
||||
ses->multi_frag_flag = 0;
|
||||
}
|
||||
|
||||
if(maccrd){
|
||||
cmd->maccrd = maccrd;
|
||||
cmd->op.cipher_op = XLR_SEC_CIPHER_MODE_PASS ;
|
||||
cmd->op.cipher_mode = XLR_SEC_CIPHER_MODE_NONE ;
|
||||
cmd->op.cipher_type = XLR_SEC_CIPHER_TYPE_NONE ;
|
||||
cmd->op.cipher_init = 0 ;
|
||||
cmd->op.cipher_offset = 0;
|
||||
|
||||
switch(maccrd->crd_alg){
|
||||
case CRYPTO_MD5:
|
||||
cmd->op.digest_type = XLR_SEC_DIGEST_TYPE_MD5 ;
|
||||
cmd->op.digest_init = XLR_SEC_DIGEST_INIT_NEWKEY ;
|
||||
cmd->op.digest_src = XLR_SEC_DIGEST_SRC_DMA ;
|
||||
cmd->op.digest_offset = 0;
|
||||
|
||||
cmd->op.cksum_type = XLR_SEC_CKSUM_TYPE_NOP ;
|
||||
cmd->op.cksum_src = XLR_SEC_CKSUM_SRC_CIPHER ;
|
||||
cmd->op.cksum_offset = 0;
|
||||
|
||||
cmd->op.pkt_hmac = XLR_SEC_LOADHMACKEY_MODE_OLD ;
|
||||
cmd->op.pkt_hash = XLR_SEC_PADHASH_PAD ;
|
||||
cmd->op.pkt_hashbytes = XLR_SEC_HASHBYTES_ALL8 ;
|
||||
cmd->op.pkt_next = XLR_SEC_NEXT_FINISH ;
|
||||
cmd->op.pkt_iv = XLR_SEC_PKT_IV_OLD ;
|
||||
cmd->op.pkt_lastword = XLR_SEC_LASTWORD_128;
|
||||
|
||||
|
||||
default:
|
||||
printf("currently not handled\n");
|
||||
}
|
||||
}
|
||||
|
||||
if(enccrd){
|
||||
cmd->enccrd = enccrd;
|
||||
|
||||
#ifdef RMI_SEC_DEBUG
|
||||
xlr_sec_print_data(crp);
|
||||
#endif
|
||||
|
||||
if(enccrd->crd_flags & CRD_F_ENCRYPT){
|
||||
cmd->op.cipher_op = XLR_SEC_CIPHER_OP_ENCRYPT;
|
||||
}
|
||||
else
|
||||
cmd->op.cipher_op = XLR_SEC_CIPHER_OP_DECRYPT;
|
||||
|
||||
switch(enccrd->crd_alg){
|
||||
case CRYPTO_DES_CBC :
|
||||
case CRYPTO_3DES_CBC:
|
||||
if(enccrd->crd_alg == CRYPTO_DES_CBC){
|
||||
cmd->op.cipher_type = XLR_SEC_CIPHER_TYPE_DES;
|
||||
memcpy(&cmd->op.crypt_key[0],enccrd->crd_key, XLR_SEC_DES_KEY_LENGTH);
|
||||
}
|
||||
else{
|
||||
cmd->op.cipher_type = XLR_SEC_CIPHER_TYPE_3DES;
|
||||
// if(enccrd->crd_flags & CRD_F_KEY_EXPLICIT)
|
||||
{
|
||||
memcpy(&cmd->op.crypt_key[0],enccrd->crd_key, XLR_SEC_3DES_KEY_LENGTH);
|
||||
}
|
||||
}
|
||||
|
||||
cmd->op.cipher_mode = XLR_SEC_CIPHER_MODE_CBC;
|
||||
cmd->op.cipher_init = XLR_SEC_CIPHER_INIT_NK;
|
||||
cmd->op.cipher_offset = XLR_SEC_DES_IV_LENGTH;
|
||||
|
||||
cmd->op.digest_type = XLR_SEC_DIGEST_TYPE_NONE;
|
||||
cmd->op.digest_init = XLR_SEC_DIGEST_INIT_OLDKEY;
|
||||
cmd->op.digest_src = XLR_SEC_DIGEST_SRC_DMA;
|
||||
cmd->op.digest_offset = 0;
|
||||
|
||||
cmd->op.cksum_type = XLR_SEC_CKSUM_TYPE_NOP;
|
||||
cmd->op.cksum_src = XLR_SEC_CKSUM_SRC_CIPHER;
|
||||
cmd->op.cksum_offset = 0;
|
||||
|
||||
cmd->op.pkt_hmac = XLR_SEC_LOADHMACKEY_MODE_OLD;
|
||||
cmd->op.pkt_hash = XLR_SEC_PADHASH_PAD;
|
||||
cmd->op.pkt_hashbytes = XLR_SEC_HASHBYTES_ALL8;
|
||||
cmd->op.pkt_next = XLR_SEC_NEXT_FINISH;
|
||||
cmd->op.pkt_iv = XLR_SEC_PKT_IV_NEW;
|
||||
cmd->op.pkt_lastword = XLR_SEC_LASTWORD_128;
|
||||
|
||||
// if((!(enccrd->crd_flags & CRD_F_IV_PRESENT)) &&
|
||||
if( (enccrd->crd_flags & CRD_F_IV_EXPLICIT)){
|
||||
memcpy(&cmd->op.initial_vector[0],enccrd->crd_iv, XLR_SEC_DES_IV_LENGTH);
|
||||
}
|
||||
break;
|
||||
|
||||
case CRYPTO_AES_CBC:
|
||||
if(enccrd->crd_alg == CRYPTO_AES_CBC){
|
||||
cmd->op.cipher_type = XLR_SEC_CIPHER_TYPE_AES128;
|
||||
// if(enccrd->crd_flags & CRD_F_KEY_EXPLICIT)
|
||||
{
|
||||
memcpy(&cmd->op.crypt_key[0],enccrd->crd_key, XLR_SEC_AES128_KEY_LENGTH);
|
||||
}
|
||||
}
|
||||
|
||||
cmd->op.cipher_mode = XLR_SEC_CIPHER_MODE_CBC;
|
||||
cmd->op.cipher_init = XLR_SEC_CIPHER_INIT_NK;
|
||||
cmd->op.cipher_offset = XLR_SEC_AES_BLOCK_SIZE;
|
||||
|
||||
cmd->op.digest_type = XLR_SEC_DIGEST_TYPE_NONE;
|
||||
cmd->op.digest_init = XLR_SEC_DIGEST_INIT_OLDKEY;
|
||||
cmd->op.digest_src = XLR_SEC_DIGEST_SRC_DMA;
|
||||
cmd->op.digest_offset = 0;
|
||||
|
||||
cmd->op.cksum_type = XLR_SEC_CKSUM_TYPE_NOP;
|
||||
cmd->op.cksum_src = XLR_SEC_CKSUM_SRC_CIPHER;
|
||||
cmd->op.cksum_offset = 0;
|
||||
|
||||
cmd->op.pkt_hmac = XLR_SEC_LOADHMACKEY_MODE_OLD;
|
||||
cmd->op.pkt_hash = XLR_SEC_PADHASH_PAD;
|
||||
cmd->op.pkt_hashbytes = XLR_SEC_HASHBYTES_ALL8;
|
||||
cmd->op.pkt_next = XLR_SEC_NEXT_FINISH;
|
||||
cmd->op.pkt_iv = XLR_SEC_PKT_IV_NEW;
|
||||
cmd->op.pkt_lastword = XLR_SEC_LASTWORD_128;
|
||||
|
||||
// if(!(enccrd->crd_flags & CRD_F_IV_PRESENT)){
|
||||
if( (enccrd->crd_flags & CRD_F_IV_EXPLICIT)){
|
||||
memcpy(&cmd->op.initial_vector[0],enccrd->crd_iv, XLR_SEC_AES_BLOCK_SIZE);
|
||||
}
|
||||
// }
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
cmd->crp = crp;
|
||||
cmd->session_num = session;
|
||||
xlr_sec_setup(ses, cmd, (symkey_desc_pt)ses->desc_ptr);
|
||||
|
||||
return(0);
|
||||
|
||||
errout:
|
||||
if (cmd != NULL)
|
||||
free(cmd, M_DEVBUF);
|
||||
crp->crp_etype = err;
|
||||
crypto_done(crp);
|
||||
return (err);
|
||||
}
|
||||
469
sys/dev/rmi/sec/stats.h
Normal file
469
sys/dev/rmi/sec/stats.h
Normal file
|
|
@ -0,0 +1,469 @@
|
|||
/*-
|
||||
* Copyright (c) 2003-2009 RMI Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of RMI Corporation, nor the names of its contributors,
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* RMI_BSD */
|
||||
|
||||
#ifndef _STATS_H_
|
||||
#define _STATS_H_
|
||||
|
||||
typedef struct hmac_stats
|
||||
{
|
||||
unsigned long md5_count;
|
||||
unsigned long long md5_bytes;
|
||||
unsigned long sha1_count;
|
||||
unsigned long long sha1_bytes;
|
||||
unsigned long sha256_count;
|
||||
unsigned long long sha256_bytes;
|
||||
unsigned long sha384_count;
|
||||
unsigned long long sha384_bytes;
|
||||
unsigned long sha512_count;
|
||||
unsigned long long sha512_bytes;
|
||||
unsigned long gcm_count;
|
||||
unsigned long long gcm_bytes;
|
||||
unsigned long kasumi_f9_count;
|
||||
unsigned long long kasumi_f9_bytes;
|
||||
unsigned long reverts;
|
||||
unsigned long long reverts_bytes;
|
||||
} hmac_stats_t, *hmac_stats_pt;
|
||||
|
||||
typedef struct cipher_stats
|
||||
{
|
||||
unsigned long des_encrypts;
|
||||
unsigned long long des_encrypt_bytes;
|
||||
unsigned long des_decrypts;
|
||||
unsigned long long des_decrypt_bytes;
|
||||
unsigned long des3_encrypts;
|
||||
unsigned long long des3_encrypt_bytes;
|
||||
unsigned long des3_decrypts;
|
||||
unsigned long long des3_decrypt_bytes;
|
||||
unsigned long aes_encrypts;
|
||||
unsigned long long aes_encrypt_bytes;
|
||||
unsigned long aes_decrypts;
|
||||
unsigned long long aes_decrypt_bytes;
|
||||
unsigned long arc4_encrypts;
|
||||
unsigned long long arc4_encrypt_bytes;
|
||||
unsigned long arc4_decrypts;
|
||||
unsigned long long arc4_decrypt_bytes;
|
||||
unsigned long kasumi_f8_encrypts;
|
||||
unsigned long long kasumi_f8_encrypt_bytes;
|
||||
unsigned long kasumi_f8_decrypts;
|
||||
unsigned long long kasumi_f8_decrypt_bytes;
|
||||
unsigned long reverts;
|
||||
unsigned long long reverts_bytes;
|
||||
} cipher_stats_t, *cipher_stats_pt;
|
||||
|
||||
|
||||
typedef struct modexp_stats
|
||||
{
|
||||
unsigned long modexp_512s;
|
||||
unsigned long modexp_1024s;
|
||||
} modexp_stats_t, *modexp_stats_pt;
|
||||
|
||||
typedef struct ecc_stats
|
||||
{
|
||||
unsigned long ecc_mul;
|
||||
unsigned long ecc_add;
|
||||
unsigned long ecc_dbl;
|
||||
unsigned long ecc_vfy;
|
||||
unsigned long ecc_bin_mul;
|
||||
unsigned long ecc_field_bin_inv;
|
||||
unsigned long ecc_field_bin_mul;
|
||||
unsigned long ecc_field_bin_add;
|
||||
unsigned long ecc_field_add;
|
||||
unsigned long ecc_field_sub;
|
||||
unsigned long ecc_field_mul;
|
||||
unsigned long ecc_field_inv;
|
||||
unsigned long ecc_field_div;
|
||||
unsigned long ecc_field_red;
|
||||
} ecc_stats_t, *ecc_stats_pt;
|
||||
|
||||
|
||||
typedef struct opt_stats
|
||||
{
|
||||
unsigned long combined;
|
||||
unsigned long unaligned_auth_dest;
|
||||
unsigned long sym_failed;
|
||||
unsigned long modexp_failed;
|
||||
unsigned long ecc_failed;
|
||||
} opt_stats_t, *opt_stats_pt;
|
||||
|
||||
typedef struct rmisec_stats
|
||||
{
|
||||
uint32_t sent;
|
||||
uint32_t received;
|
||||
uint32_t stats_mask;
|
||||
uint32_t control_mask;
|
||||
rwlock_t rmisec_control_lock;
|
||||
rwlock_t rmisec_stats_lock;
|
||||
char clear_start[0];
|
||||
uint64_t wait_time;
|
||||
uint32_t max_wait_time;
|
||||
uint32_t maxsnd_wait_time;
|
||||
uint32_t wait_count;
|
||||
hmac_stats_t hmac;
|
||||
cipher_stats_t cipher;
|
||||
modexp_stats_t modexp;
|
||||
ecc_stats_t ecc;
|
||||
opt_stats_t opt;
|
||||
} rmisec_stats_t, *rmisec_stats_pt;
|
||||
|
||||
|
||||
/* stats routines */
|
||||
|
||||
static void inline phxdrv_record_sent(rmisec_stats_pt stats)
|
||||
{
|
||||
write_lock(&stats->rmisec_stats_lock);
|
||||
stats->sent++;
|
||||
write_unlock(&stats->rmisec_stats_lock);
|
||||
}
|
||||
|
||||
static void inline phxdrv_record_received(rmisec_stats_pt stats)
|
||||
{
|
||||
write_lock(&stats->rmisec_stats_lock);
|
||||
stats->received++;
|
||||
write_unlock(&stats->rmisec_stats_lock);
|
||||
}
|
||||
|
||||
|
||||
static void inline phxdrv_record_des(rmisec_stats_pt stats, int enc,
|
||||
int nbytes)
|
||||
{
|
||||
if (stats->stats_mask & PHXDRV_PROFILE_DES) {
|
||||
write_lock(&stats->rmisec_stats_lock);
|
||||
if (enc) {
|
||||
stats->cipher.des_encrypts++;
|
||||
stats->cipher.des_encrypt_bytes += nbytes;
|
||||
}
|
||||
else {
|
||||
stats->cipher.des_decrypts++;
|
||||
stats->cipher.des_decrypt_bytes += nbytes;
|
||||
}
|
||||
write_unlock(&stats->rmisec_stats_lock);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void inline phxdrv_record_3des(rmisec_stats_pt stats, int enc,
|
||||
int nbytes)
|
||||
{
|
||||
if (stats->stats_mask & PHXDRV_PROFILE_3DES) {
|
||||
write_lock(&stats->rmisec_stats_lock);
|
||||
if (enc) {
|
||||
stats->cipher.des3_encrypts++;
|
||||
stats->cipher.des3_encrypt_bytes += nbytes;
|
||||
}
|
||||
else {
|
||||
stats->cipher.des3_decrypts++;
|
||||
stats->cipher.des3_decrypt_bytes += nbytes;
|
||||
}
|
||||
write_unlock(&stats->rmisec_stats_lock);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void inline phxdrv_record_aes(rmisec_stats_pt stats, int enc,
|
||||
int nbytes)
|
||||
{
|
||||
if (stats->stats_mask & PHXDRV_PROFILE_AES) {
|
||||
write_lock(&stats->rmisec_stats_lock);
|
||||
if (enc) {
|
||||
stats->cipher.aes_encrypts++;
|
||||
stats->cipher.aes_encrypt_bytes += nbytes;
|
||||
}
|
||||
else {
|
||||
stats->cipher.aes_decrypts++;
|
||||
stats->cipher.aes_decrypt_bytes += nbytes;
|
||||
}
|
||||
write_unlock(&stats->rmisec_stats_lock);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void inline phxdrv_record_arc4(rmisec_stats_pt stats, int enc,
|
||||
int nbytes)
|
||||
{
|
||||
if (stats->stats_mask & PHXDRV_PROFILE_ARC4) {
|
||||
write_lock(&stats->rmisec_stats_lock);
|
||||
if (enc) {
|
||||
stats->cipher.arc4_encrypts++;
|
||||
stats->cipher.arc4_encrypt_bytes += nbytes;
|
||||
}
|
||||
else {
|
||||
stats->cipher.arc4_decrypts++;
|
||||
stats->cipher.arc4_decrypt_bytes += nbytes;
|
||||
}
|
||||
write_unlock(&stats->rmisec_stats_lock);
|
||||
}
|
||||
}
|
||||
|
||||
static void inline phxdrv_record_kasumi_f8(rmisec_stats_pt stats, int enc,
|
||||
int nbytes)
|
||||
{
|
||||
if (stats->stats_mask & PHXDRV_PROFILE_KASUMI_F8) {
|
||||
write_lock(&stats->rmisec_stats_lock);
|
||||
if (enc) {
|
||||
stats->cipher.kasumi_f8_encrypts++;
|
||||
stats->cipher.kasumi_f8_encrypt_bytes += nbytes;
|
||||
}
|
||||
else {
|
||||
stats->cipher.kasumi_f8_decrypts++;
|
||||
stats->cipher.kasumi_f8_decrypt_bytes += nbytes;
|
||||
}
|
||||
write_unlock(&stats->rmisec_stats_lock);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void inline phxdrv_record_modexp(rmisec_stats_pt stats,
|
||||
int blksize)
|
||||
{
|
||||
if (stats->stats_mask & PHXDRV_PROFILE_MODEXP) {
|
||||
write_lock(&stats->rmisec_stats_lock);
|
||||
if (blksize == 512) {
|
||||
stats->modexp.modexp_512s++;
|
||||
}
|
||||
if (blksize == 1024) {
|
||||
stats->modexp.modexp_1024s++;
|
||||
}
|
||||
write_unlock(&stats->rmisec_stats_lock);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void inline phxdrv_record_ecc(rmisec_stats_pt stats, PHX_ECC_OP op)
|
||||
{
|
||||
if (stats->stats_mask & PHXDRV_PROFILE_ECC) {
|
||||
write_lock(&stats->rmisec_stats_lock);
|
||||
switch (op) {
|
||||
case PHX_ECC_NOP:
|
||||
break;
|
||||
case PHX_ECC_MUL:
|
||||
stats->ecc.ecc_mul++;
|
||||
break;
|
||||
case PHX_ECC_BIN_MUL:
|
||||
stats->ecc.ecc_bin_mul++;
|
||||
break;
|
||||
case PHX_ECC_ADD:
|
||||
stats->ecc.ecc_add++;
|
||||
break;
|
||||
case PHX_ECC_DBL:
|
||||
stats->ecc.ecc_dbl++;
|
||||
break;
|
||||
case PHX_ECC_VFY:
|
||||
stats->ecc.ecc_vfy++;
|
||||
break;
|
||||
case PHX_ECC_FIELD_BIN_INV:
|
||||
stats->ecc.ecc_field_bin_inv++;
|
||||
break;
|
||||
case PHX_ECC_FIELD_BIN_MUL:
|
||||
stats->ecc.ecc_field_bin_mul++;
|
||||
break;
|
||||
case PHX_ECC_FIELD_BIN_ADD:
|
||||
stats->ecc.ecc_field_bin_add++;
|
||||
break;
|
||||
case PHX_ECC_FIELD_ADD:
|
||||
stats->ecc.ecc_field_add++;
|
||||
break;
|
||||
case PHX_ECC_FIELD_SUB:
|
||||
stats->ecc.ecc_field_sub++;
|
||||
break;
|
||||
case PHX_ECC_FIELD_MUL:
|
||||
stats->ecc.ecc_field_mul++;
|
||||
break;
|
||||
case PHX_ECC_FIELD_INV:
|
||||
stats->ecc.ecc_field_inv++;
|
||||
break;
|
||||
case PHX_ECC_FIELD_DIV:
|
||||
stats->ecc.ecc_field_div++;
|
||||
break;
|
||||
case PHX_ECC_FIELD_RED:
|
||||
stats->ecc.ecc_field_red++;
|
||||
break;
|
||||
case PHX_ECC_FIELD:
|
||||
case PHX_ECC_BIN:
|
||||
break;
|
||||
}
|
||||
write_unlock(&stats->rmisec_stats_lock);
|
||||
}
|
||||
}
|
||||
|
||||
static void inline phxdrv_record_cipher_revert(rmisec_stats_pt stats,
|
||||
int nbytes)
|
||||
{
|
||||
if (stats->stats_mask & PHXDRV_PROFILE_CPHR_REVERTS) {
|
||||
write_lock(&stats->rmisec_stats_lock);
|
||||
stats->cipher.reverts++;
|
||||
stats->cipher.reverts_bytes += nbytes;
|
||||
write_unlock(&stats->rmisec_stats_lock);
|
||||
}
|
||||
}
|
||||
|
||||
static void inline phxdrv_record_hmac_revert(rmisec_stats_pt stats,
|
||||
int nbytes)
|
||||
{
|
||||
if (stats->stats_mask & PHXDRV_PROFILE_HMAC_REVERTS) {
|
||||
write_lock(&stats->rmisec_stats_lock);
|
||||
stats->hmac.reverts++;
|
||||
stats->hmac.reverts_bytes += nbytes;
|
||||
write_unlock(&stats->rmisec_stats_lock);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void inline phxdrv_record_md5(rmisec_stats_pt stats,
|
||||
int nbytes)
|
||||
{
|
||||
if (stats->stats_mask & PHXDRV_PROFILE_MD5) {
|
||||
write_lock(&stats->rmisec_stats_lock);
|
||||
stats->hmac.md5_count++;
|
||||
stats->hmac.md5_bytes += nbytes;
|
||||
write_unlock(&stats->rmisec_stats_lock);
|
||||
}
|
||||
}
|
||||
|
||||
static void inline phxdrv_record_sha1(rmisec_stats_pt stats,
|
||||
int nbytes)
|
||||
{
|
||||
if (stats->stats_mask & PHXDRV_PROFILE_SHA1) {
|
||||
write_lock(&stats->rmisec_stats_lock);
|
||||
stats->hmac.sha1_count++;
|
||||
stats->hmac.sha1_bytes += nbytes;
|
||||
write_unlock(&stats->rmisec_stats_lock);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void inline phxdrv_record_sha256(rmisec_stats_pt stats,
|
||||
int nbytes)
|
||||
{
|
||||
if (stats->stats_mask & PHXDRV_PROFILE_SHA256) {
|
||||
write_lock(&stats->rmisec_stats_lock);
|
||||
stats->hmac.sha256_count++;
|
||||
stats->hmac.sha256_bytes += nbytes;
|
||||
write_unlock(&stats->rmisec_stats_lock);
|
||||
}
|
||||
}
|
||||
|
||||
static void inline phxdrv_record_sha384(rmisec_stats_pt stats,
|
||||
int nbytes)
|
||||
{
|
||||
if (stats->stats_mask & PHXDRV_PROFILE_SHA384) {
|
||||
write_lock(&stats->rmisec_stats_lock);
|
||||
stats->hmac.sha384_count++;
|
||||
stats->hmac.sha384_bytes += nbytes;
|
||||
write_unlock(&stats->rmisec_stats_lock);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void inline phxdrv_record_sha512(rmisec_stats_pt stats,
|
||||
int nbytes)
|
||||
{
|
||||
if (stats->stats_mask & PHXDRV_PROFILE_SHA512) {
|
||||
write_lock(&stats->rmisec_stats_lock);
|
||||
stats->hmac.sha512_count++;
|
||||
stats->hmac.sha512_bytes += nbytes;
|
||||
write_unlock(&stats->rmisec_stats_lock);
|
||||
}
|
||||
}
|
||||
|
||||
static void inline phxdrv_record_gcm(rmisec_stats_pt stats,
|
||||
int nbytes)
|
||||
{
|
||||
if (stats->stats_mask & PHXDRV_PROFILE_GCM) {
|
||||
write_lock(&stats->rmisec_stats_lock);
|
||||
stats->hmac.gcm_count++;
|
||||
stats->hmac.gcm_bytes += nbytes;
|
||||
write_unlock(&stats->rmisec_stats_lock);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void inline phxdrv_record_kasumi_f9(rmisec_stats_pt stats,
|
||||
int nbytes)
|
||||
{
|
||||
if (stats->stats_mask & PHXDRV_PROFILE_KASUMI_F9) {
|
||||
write_lock(&stats->rmisec_stats_lock);
|
||||
stats->hmac.kasumi_f9_count++;
|
||||
stats->hmac.kasumi_f9_bytes += nbytes;
|
||||
write_unlock(&stats->rmisec_stats_lock);
|
||||
}
|
||||
}
|
||||
|
||||
static void inline phxdrv_record_unaligned_auth_dest(rmisec_stats_pt stats,
|
||||
int nbytes)
|
||||
{
|
||||
if (stats->stats_mask & PHXDRV_PROFILE_UNALIGNED_AUTH_DEST) {
|
||||
write_lock(&stats->rmisec_stats_lock);
|
||||
stats->opt.unaligned_auth_dest++;
|
||||
write_unlock(&stats->rmisec_stats_lock);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void inline phxdrv_record_combined(rmisec_stats_pt stats,
|
||||
int nbytes)
|
||||
{
|
||||
if (stats->stats_mask & PHXDRV_PROFILE_COMBINED) {
|
||||
write_lock(&stats->rmisec_stats_lock);
|
||||
stats->opt.combined++;
|
||||
write_unlock(&stats->rmisec_stats_lock);
|
||||
}
|
||||
}
|
||||
|
||||
static void inline phxdrv_record_sym_failed(rmisec_stats_pt stats,
|
||||
int nbytes)
|
||||
{
|
||||
if (stats->stats_mask & PHXDRV_PROFILE_COMBINED) {
|
||||
write_lock(&stats->rmisec_stats_lock);
|
||||
stats->opt.sym_failed++;
|
||||
write_unlock(&stats->rmisec_stats_lock);
|
||||
}
|
||||
}
|
||||
|
||||
static void inline phxdrv_record_modexp_failed(rmisec_stats_pt stats,
|
||||
int nbytes)
|
||||
{
|
||||
if (stats->stats_mask & PHXDRV_PROFILE_COMBINED) {
|
||||
write_lock(&stats->rmisec_stats_lock);
|
||||
stats->opt.modexp_failed++;
|
||||
write_unlock(&stats->rmisec_stats_lock);
|
||||
}
|
||||
}
|
||||
|
||||
static void inline phxdrv_record_ecc_failed(rmisec_stats_pt stats,
|
||||
int nbytes)
|
||||
{
|
||||
if (stats->stats_mask & PHXDRV_PROFILE_COMBINED) {
|
||||
write_lock(&stats->rmisec_stats_lock);
|
||||
stats->opt.ecc_failed++;
|
||||
write_unlock(&stats->rmisec_stats_lock);
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
53
sys/dev/rmi/xlr/atx_cpld.h
Normal file
53
sys/dev/rmi/xlr/atx_cpld.h
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
/*-
|
||||
* Copyright (c) 2003-2009 RMI Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of RMI Corporation, nor the names of its contributors,
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* RMI_BSD */
|
||||
#ifndef _RMI_ATX_CPLD_H_
|
||||
#define _RMI_ATX_CPLD_H_
|
||||
|
||||
/*
|
||||
* bit_0 : xgs0 phy reset, bit_1 : xgs1 phy reset, bit_2 : HT reset, bit_3 :
|
||||
* RTC reset, bit_4 : gmac phy soft reset, bit_5 : gmac phy hard reset, bit_6
|
||||
* : board reset, bit_7 : reserved
|
||||
*/
|
||||
#define ATX_CPLD_RESET_1 2
|
||||
|
||||
/*
|
||||
* bit_0_2 : reserved, bit_3 : turn off xpak_0 tx, bit_4 : turn off xpak_1
|
||||
* tx, bit_5 : HT stop (active low), bit_6 : flash program enable, bit_7 :
|
||||
* compact flash io mode
|
||||
*/
|
||||
#define ATX_CPLD_MISC_CTRL 8
|
||||
|
||||
/*
|
||||
* bit_0 : reset tcam, bit_1 : reset xpak_0 module, bit_2 : reset xpak_1
|
||||
* module, bit_3_7 : reserved
|
||||
*/
|
||||
#define ATX_CPLD_RESET_2 9
|
||||
|
||||
#endif /* _RMI_ATX_CPLD_H_ */
|
||||
2815
sys/dev/rmi/xlr/rge.c
Normal file
2815
sys/dev/rmi/xlr/rge.c
Normal file
File diff suppressed because it is too large
Load diff
978
sys/dev/rmi/xlr/rge.h
Normal file
978
sys/dev/rmi/xlr/rge.h
Normal file
|
|
@ -0,0 +1,978 @@
|
|||
/*-
|
||||
* Copyright (c) 2003-2009 RMI Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of RMI Corporation, nor the names of its contributors,
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* RMI_BSD */
|
||||
#ifndef _RMI_RGE_H_
|
||||
#define _RMI_RGE_H_
|
||||
|
||||
/* #define MAC_SPLIT_MODE */
|
||||
|
||||
#define MAC_SPACING 0x400
|
||||
#define XGMAC_SPACING 0x400
|
||||
|
||||
/* PE-MCXMAC register and bit field definitions */
|
||||
#define R_MAC_CONFIG_1 0x00
|
||||
#define O_MAC_CONFIG_1__srst 31
|
||||
#define O_MAC_CONFIG_1__simr 30
|
||||
#define O_MAC_CONFIG_1__hrrmc 18
|
||||
#define W_MAC_CONFIG_1__hrtmc 2
|
||||
#define O_MAC_CONFIG_1__hrrfn 16
|
||||
#define W_MAC_CONFIG_1__hrtfn 2
|
||||
#define O_MAC_CONFIG_1__intlb 8
|
||||
#define O_MAC_CONFIG_1__rxfc 5
|
||||
#define O_MAC_CONFIG_1__txfc 4
|
||||
#define O_MAC_CONFIG_1__srxen 3
|
||||
#define O_MAC_CONFIG_1__rxen 2
|
||||
#define O_MAC_CONFIG_1__stxen 1
|
||||
#define O_MAC_CONFIG_1__txen 0
|
||||
#define R_MAC_CONFIG_2 0x01
|
||||
#define O_MAC_CONFIG_2__prlen 12
|
||||
#define W_MAC_CONFIG_2__prlen 4
|
||||
#define O_MAC_CONFIG_2__speed 8
|
||||
#define W_MAC_CONFIG_2__speed 2
|
||||
#define O_MAC_CONFIG_2__hugen 5
|
||||
#define O_MAC_CONFIG_2__flchk 4
|
||||
#define O_MAC_CONFIG_2__crce 1
|
||||
#define O_MAC_CONFIG_2__fulld 0
|
||||
#define R_IPG_IFG 0x02
|
||||
#define O_IPG_IFG__ipgr1 24
|
||||
#define W_IPG_IFG__ipgr1 7
|
||||
#define O_IPG_IFG__ipgr2 16
|
||||
#define W_IPG_IFG__ipgr2 7
|
||||
#define O_IPG_IFG__mifg 8
|
||||
#define W_IPG_IFG__mifg 8
|
||||
#define O_IPG_IFG__ipgt 0
|
||||
#define W_IPG_IFG__ipgt 7
|
||||
#define R_HALF_DUPLEX 0x03
|
||||
#define O_HALF_DUPLEX__abebt 24
|
||||
#define W_HALF_DUPLEX__abebt 4
|
||||
#define O_HALF_DUPLEX__abebe 19
|
||||
#define O_HALF_DUPLEX__bpnb 18
|
||||
#define O_HALF_DUPLEX__nobo 17
|
||||
#define O_HALF_DUPLEX__edxsdfr 16
|
||||
#define O_HALF_DUPLEX__retry 12
|
||||
#define W_HALF_DUPLEX__retry 4
|
||||
#define O_HALF_DUPLEX__lcol 0
|
||||
#define W_HALF_DUPLEX__lcol 10
|
||||
#define R_MAXIMUM_FRAME_LENGTH 0x04
|
||||
#define O_MAXIMUM_FRAME_LENGTH__maxf 0
|
||||
#define W_MAXIMUM_FRAME_LENGTH__maxf 16
|
||||
#define R_TEST 0x07
|
||||
#define O_TEST__mbof 3
|
||||
#define O_TEST__rthdf 2
|
||||
#define O_TEST__tpause 1
|
||||
#define O_TEST__sstct 0
|
||||
#define R_MII_MGMT_CONFIG 0x08
|
||||
#define O_MII_MGMT_CONFIG__scinc 5
|
||||
#define O_MII_MGMT_CONFIG__spre 4
|
||||
#define O_MII_MGMT_CONFIG__clks 3
|
||||
#define W_MII_MGMT_CONFIG__clks 3
|
||||
#define R_MII_MGMT_COMMAND 0x09
|
||||
#define O_MII_MGMT_COMMAND__scan 1
|
||||
#define O_MII_MGMT_COMMAND__rstat 0
|
||||
#define R_MII_MGMT_ADDRESS 0x0A
|
||||
#define O_MII_MGMT_ADDRESS__fiad 8
|
||||
#define W_MII_MGMT_ADDRESS__fiad 5
|
||||
#define O_MII_MGMT_ADDRESS__fgad 5
|
||||
#define W_MII_MGMT_ADDRESS__fgad 0
|
||||
#define R_MII_MGMT_WRITE_DATA 0x0B
|
||||
#define O_MII_MGMT_WRITE_DATA__ctld 0
|
||||
#define W_MII_MGMT_WRITE_DATA__ctld 16
|
||||
#define R_MII_MGMT_STATUS 0x0C
|
||||
#define R_MII_MGMT_INDICATORS 0x0D
|
||||
#define O_MII_MGMT_INDICATORS__nvalid 2
|
||||
#define O_MII_MGMT_INDICATORS__scan 1
|
||||
#define O_MII_MGMT_INDICATORS__busy 0
|
||||
#define R_INTERFACE_CONTROL 0x0E
|
||||
#define O_INTERFACE_CONTROL__hrstint 31
|
||||
#define O_INTERFACE_CONTROL__tbimode 27
|
||||
#define O_INTERFACE_CONTROL__ghdmode 26
|
||||
#define O_INTERFACE_CONTROL__lhdmode 25
|
||||
#define O_INTERFACE_CONTROL__phymod 24
|
||||
#define O_INTERFACE_CONTROL__hrrmi 23
|
||||
#define O_INTERFACE_CONTROL__rspd 16
|
||||
#define O_INTERFACE_CONTROL__hr100 15
|
||||
#define O_INTERFACE_CONTROL__frcq 10
|
||||
#define O_INTERFACE_CONTROL__nocfr 9
|
||||
#define O_INTERFACE_CONTROL__dlfct 8
|
||||
#define O_INTERFACE_CONTROL__enjab 0
|
||||
#define R_INTERFACE_STATUS 0x0F
|
||||
#define O_INTERFACE_STATUS__xsdfr 9
|
||||
#define O_INTERFACE_STATUS__ssrr 8
|
||||
#define W_INTERFACE_STATUS__ssrr 5
|
||||
#define O_INTERFACE_STATUS__miilf 3
|
||||
#define O_INTERFACE_STATUS__locar 2
|
||||
#define O_INTERFACE_STATUS__sqerr 1
|
||||
#define O_INTERFACE_STATUS__jabber 0
|
||||
#define R_STATION_ADDRESS_LS 0x10
|
||||
#define R_STATION_ADDRESS_MS 0x11
|
||||
|
||||
/* A-XGMAC register and bit field definitions */
|
||||
#define R_XGMAC_CONFIG_0 0x00
|
||||
#define O_XGMAC_CONFIG_0__hstmacrst 31
|
||||
#define O_XGMAC_CONFIG_0__hstrstrctl 23
|
||||
#define O_XGMAC_CONFIG_0__hstrstrfn 22
|
||||
#define O_XGMAC_CONFIG_0__hstrsttctl 18
|
||||
#define O_XGMAC_CONFIG_0__hstrsttfn 17
|
||||
#define O_XGMAC_CONFIG_0__hstrstmiim 16
|
||||
#define O_XGMAC_CONFIG_0__hstloopback 8
|
||||
#define R_XGMAC_CONFIG_1 0x01
|
||||
#define O_XGMAC_CONFIG_1__hsttctlen 31
|
||||
#define O_XGMAC_CONFIG_1__hsttfen 30
|
||||
#define O_XGMAC_CONFIG_1__hstrctlen 29
|
||||
#define O_XGMAC_CONFIG_1__hstrfen 28
|
||||
#define O_XGMAC_CONFIG_1__tfen 26
|
||||
#define O_XGMAC_CONFIG_1__rfen 24
|
||||
#define O_XGMAC_CONFIG_1__hstrctlshrtp 12
|
||||
#define O_XGMAC_CONFIG_1__hstdlyfcstx 10
|
||||
#define W_XGMAC_CONFIG_1__hstdlyfcstx 2
|
||||
#define O_XGMAC_CONFIG_1__hstdlyfcsrx 8
|
||||
#define W_XGMAC_CONFIG_1__hstdlyfcsrx 2
|
||||
#define O_XGMAC_CONFIG_1__hstppen 7
|
||||
#define O_XGMAC_CONFIG_1__hstbytswp 6
|
||||
#define O_XGMAC_CONFIG_1__hstdrplt64 5
|
||||
#define O_XGMAC_CONFIG_1__hstprmscrx 4
|
||||
#define O_XGMAC_CONFIG_1__hstlenchk 3
|
||||
#define O_XGMAC_CONFIG_1__hstgenfcs 2
|
||||
#define O_XGMAC_CONFIG_1__hstpadmode 0
|
||||
#define W_XGMAC_CONFIG_1__hstpadmode 2
|
||||
#define R_XGMAC_CONFIG_2 0x02
|
||||
#define O_XGMAC_CONFIG_2__hsttctlfrcp 31
|
||||
#define O_XGMAC_CONFIG_2__hstmlnkflth 27
|
||||
#define O_XGMAC_CONFIG_2__hstalnkflth 26
|
||||
#define O_XGMAC_CONFIG_2__rflnkflt 24
|
||||
#define W_XGMAC_CONFIG_2__rflnkflt 2
|
||||
#define O_XGMAC_CONFIG_2__hstipgextmod 16
|
||||
#define W_XGMAC_CONFIG_2__hstipgextmod 5
|
||||
#define O_XGMAC_CONFIG_2__hstrctlfrcp 15
|
||||
#define O_XGMAC_CONFIG_2__hstipgexten 5
|
||||
#define O_XGMAC_CONFIG_2__hstmipgext 0
|
||||
#define W_XGMAC_CONFIG_2__hstmipgext 5
|
||||
#define R_XGMAC_CONFIG_3 0x03
|
||||
#define O_XGMAC_CONFIG_3__hstfltrfrm 31
|
||||
#define W_XGMAC_CONFIG_3__hstfltrfrm 16
|
||||
#define O_XGMAC_CONFIG_3__hstfltrfrmdc 15
|
||||
#define W_XGMAC_CONFIG_3__hstfltrfrmdc 16
|
||||
#define R_XGMAC_STATION_ADDRESS_LS 0x04
|
||||
#define O_XGMAC_STATION_ADDRESS_LS__hstmacadr0 0
|
||||
#define W_XGMAC_STATION_ADDRESS_LS__hstmacadr0 32
|
||||
#define R_XGMAC_STATION_ADDRESS_MS 0x05
|
||||
#define R_XGMAC_MAX_FRAME_LEN 0x08
|
||||
#define O_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 16
|
||||
#define W_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 14
|
||||
#define O_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 0
|
||||
#define W_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 16
|
||||
#define R_XGMAC_REV_LEVEL 0x0B
|
||||
#define O_XGMAC_REV_LEVEL__revlvl 0
|
||||
#define W_XGMAC_REV_LEVEL__revlvl 15
|
||||
#define R_XGMAC_MIIM_COMMAND 0x10
|
||||
#define O_XGMAC_MIIM_COMMAND__hstldcmd 3
|
||||
#define O_XGMAC_MIIM_COMMAND__hstmiimcmd 0
|
||||
#define W_XGMAC_MIIM_COMMAND__hstmiimcmd 3
|
||||
#define R_XGMAC_MIIM_FILED 0x11
|
||||
#define O_XGMAC_MIIM_FILED__hststfield 30
|
||||
#define W_XGMAC_MIIM_FILED__hststfield 2
|
||||
#define O_XGMAC_MIIM_FILED__hstopfield 28
|
||||
#define W_XGMAC_MIIM_FILED__hstopfield 2
|
||||
#define O_XGMAC_MIIM_FILED__hstphyadx 23
|
||||
#define W_XGMAC_MIIM_FILED__hstphyadx 5
|
||||
#define O_XGMAC_MIIM_FILED__hstregadx 18
|
||||
#define W_XGMAC_MIIM_FILED__hstregadx 5
|
||||
#define O_XGMAC_MIIM_FILED__hsttafield 16
|
||||
#define W_XGMAC_MIIM_FILED__hsttafield 2
|
||||
#define O_XGMAC_MIIM_FILED__miimrddat 0
|
||||
#define W_XGMAC_MIIM_FILED__miimrddat 16
|
||||
#define R_XGMAC_MIIM_CONFIG 0x12
|
||||
#define O_XGMAC_MIIM_CONFIG__hstnopram 7
|
||||
#define O_XGMAC_MIIM_CONFIG__hstclkdiv 0
|
||||
#define W_XGMAC_MIIM_CONFIG__hstclkdiv 7
|
||||
#define R_XGMAC_MIIM_LINK_FAIL_VECTOR 0x13
|
||||
#define O_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 0
|
||||
#define W_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 32
|
||||
#define R_XGMAC_MIIM_INDICATOR 0x14
|
||||
#define O_XGMAC_MIIM_INDICATOR__miimphylf 4
|
||||
#define O_XGMAC_MIIM_INDICATOR__miimmoncplt 3
|
||||
#define O_XGMAC_MIIM_INDICATOR__miimmonvld 2
|
||||
#define O_XGMAC_MIIM_INDICATOR__miimmon 1
|
||||
#define O_XGMAC_MIIM_INDICATOR__miimbusy 0
|
||||
|
||||
/* Glue logic register and bit field definitions */
|
||||
#define R_MAC_ADDR0 0x50
|
||||
#define R_MAC_ADDR1 0x52
|
||||
#define R_MAC_ADDR2 0x54
|
||||
#define R_MAC_ADDR3 0x56
|
||||
#define R_MAC_ADDR_MASK2 0x58
|
||||
#define R_MAC_ADDR_MASK3 0x5A
|
||||
#define R_MAC_FILTER_CONFIG 0x5C
|
||||
#define O_MAC_FILTER_CONFIG__BROADCAST_EN 10
|
||||
#define O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN 9
|
||||
#define O_MAC_FILTER_CONFIG__ALL_MCAST_EN 8
|
||||
#define O_MAC_FILTER_CONFIG__ALL_UCAST_EN 7
|
||||
#define O_MAC_FILTER_CONFIG__HASH_MCAST_EN 6
|
||||
#define O_MAC_FILTER_CONFIG__HASH_UCAST_EN 5
|
||||
#define O_MAC_FILTER_CONFIG__ADDR_MATCH_DISC 4
|
||||
#define O_MAC_FILTER_CONFIG__MAC_ADDR3_VALID 3
|
||||
#define O_MAC_FILTER_CONFIG__MAC_ADDR2_VALID 2
|
||||
#define O_MAC_FILTER_CONFIG__MAC_ADDR1_VALID 1
|
||||
#define O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID 0
|
||||
#define R_HASH_TABLE_VECTOR 0x30
|
||||
#define R_TX_CONTROL 0x0A0
|
||||
#define O_TX_CONTROL__Tx15Halt 31
|
||||
#define O_TX_CONTROL__Tx14Halt 30
|
||||
#define O_TX_CONTROL__Tx13Halt 29
|
||||
#define O_TX_CONTROL__Tx12Halt 28
|
||||
#define O_TX_CONTROL__Tx11Halt 27
|
||||
#define O_TX_CONTROL__Tx10Halt 26
|
||||
#define O_TX_CONTROL__Tx9Halt 25
|
||||
#define O_TX_CONTROL__Tx8Halt 24
|
||||
#define O_TX_CONTROL__Tx7Halt 23
|
||||
#define O_TX_CONTROL__Tx6Halt 22
|
||||
#define O_TX_CONTROL__Tx5Halt 21
|
||||
#define O_TX_CONTROL__Tx4Halt 20
|
||||
#define O_TX_CONTROL__Tx3Halt 19
|
||||
#define O_TX_CONTROL__Tx2Halt 18
|
||||
#define O_TX_CONTROL__Tx1Halt 17
|
||||
#define O_TX_CONTROL__Tx0Halt 16
|
||||
#define O_TX_CONTROL__TxIdle 15
|
||||
#define O_TX_CONTROL__TxEnable 14
|
||||
#define O_TX_CONTROL__TxThreshold 0
|
||||
#define W_TX_CONTROL__TxThreshold 14
|
||||
#define R_RX_CONTROL 0x0A1
|
||||
#define O_RX_CONTROL__RGMII 10
|
||||
#define O_RX_CONTROL__RxHalt 1
|
||||
#define O_RX_CONTROL__RxEnable 0
|
||||
#define R_DESC_PACK_CTRL 0x0A2
|
||||
#define O_DESC_PACK_CTRL__ByteOffset 17
|
||||
#define W_DESC_PACK_CTRL__ByteOffset 3
|
||||
#define O_DESC_PACK_CTRL__PrePadEnable 16
|
||||
#define O_DESC_PACK_CTRL__MaxEntry 14
|
||||
#define W_DESC_PACK_CTRL__MaxEntry 2
|
||||
#define O_DESC_PACK_CTRL__RegularSize 0
|
||||
#define W_DESC_PACK_CTRL__RegularSize 14
|
||||
#define R_STATCTRL 0x0A3
|
||||
#define O_STATCTRL__OverFlowEn 4
|
||||
#define O_STATCTRL__GIG 3
|
||||
#define O_STATCTRL__Sten 2
|
||||
#define O_STATCTRL__ClrCnt 1
|
||||
#define O_STATCTRL__AutoZ 0
|
||||
#define R_L2ALLOCCTRL 0x0A4
|
||||
#define O_L2ALLOCCTRL__TxL2Allocate 9
|
||||
#define W_L2ALLOCCTRL__TxL2Allocate 9
|
||||
#define O_L2ALLOCCTRL__RxL2Allocate 0
|
||||
#define W_L2ALLOCCTRL__RxL2Allocate 9
|
||||
#define R_INTMASK 0x0A5
|
||||
#define O_INTMASK__Spi4TxError 28
|
||||
#define O_INTMASK__Spi4RxError 27
|
||||
#define O_INTMASK__RGMIIHalfDupCollision 27
|
||||
#define O_INTMASK__Abort 26
|
||||
#define O_INTMASK__Underrun 25
|
||||
#define O_INTMASK__DiscardPacket 24
|
||||
#define O_INTMASK__AsyncFifoFull 23
|
||||
#define O_INTMASK__TagFull 22
|
||||
#define O_INTMASK__Class3Full 21
|
||||
#define O_INTMASK__C3EarlyFull 20
|
||||
#define O_INTMASK__Class2Full 19
|
||||
#define O_INTMASK__C2EarlyFull 18
|
||||
#define O_INTMASK__Class1Full 17
|
||||
#define O_INTMASK__C1EarlyFull 16
|
||||
#define O_INTMASK__Class0Full 15
|
||||
#define O_INTMASK__C0EarlyFull 14
|
||||
#define O_INTMASK__RxDataFull 13
|
||||
#define O_INTMASK__RxEarlyFull 12
|
||||
#define O_INTMASK__RFreeEmpty 9
|
||||
#define O_INTMASK__RFEarlyEmpty 8
|
||||
#define O_INTMASK__P2PSpillEcc 7
|
||||
#define O_INTMASK__FreeDescFull 5
|
||||
#define O_INTMASK__FreeEarlyFull 4
|
||||
#define O_INTMASK__TxFetchError 3
|
||||
#define O_INTMASK__StatCarry 2
|
||||
#define O_INTMASK__MDInt 1
|
||||
#define O_INTMASK__TxIllegal 0
|
||||
#define R_INTREG 0x0A6
|
||||
#define O_INTREG__Spi4TxError 28
|
||||
#define O_INTREG__Spi4RxError 27
|
||||
#define O_INTREG__RGMIIHalfDupCollision 27
|
||||
#define O_INTREG__Abort 26
|
||||
#define O_INTREG__Underrun 25
|
||||
#define O_INTREG__DiscardPacket 24
|
||||
#define O_INTREG__AsyncFifoFull 23
|
||||
#define O_INTREG__TagFull 22
|
||||
#define O_INTREG__Class3Full 21
|
||||
#define O_INTREG__C3EarlyFull 20
|
||||
#define O_INTREG__Class2Full 19
|
||||
#define O_INTREG__C2EarlyFull 18
|
||||
#define O_INTREG__Class1Full 17
|
||||
#define O_INTREG__C1EarlyFull 16
|
||||
#define O_INTREG__Class0Full 15
|
||||
#define O_INTREG__C0EarlyFull 14
|
||||
#define O_INTREG__RxDataFull 13
|
||||
#define O_INTREG__RxEarlyFull 12
|
||||
#define O_INTREG__RFreeEmpty 9
|
||||
#define O_INTREG__RFEarlyEmpty 8
|
||||
#define O_INTREG__P2PSpillEcc 7
|
||||
#define O_INTREG__FreeDescFull 5
|
||||
#define O_INTREG__FreeEarlyFull 4
|
||||
#define O_INTREG__TxFetchError 3
|
||||
#define O_INTREG__StatCarry 2
|
||||
#define O_INTREG__MDInt 1
|
||||
#define O_INTREG__TxIllegal 0
|
||||
#define R_TXRETRY 0x0A7
|
||||
#define O_TXRETRY__CollisionRetry 6
|
||||
#define O_TXRETRY__BusErrorRetry 5
|
||||
#define O_TXRETRY__UnderRunRetry 4
|
||||
#define O_TXRETRY__Retries 0
|
||||
#define W_TXRETRY__Retries 4
|
||||
#define R_CORECONTROL 0x0A8
|
||||
#define O_CORECONTROL__ErrorThread 4
|
||||
#define W_CORECONTROL__ErrorThread 7
|
||||
#define O_CORECONTROL__Shutdown 2
|
||||
#define O_CORECONTROL__Speed 0
|
||||
#define W_CORECONTROL__Speed 2
|
||||
#define R_BYTEOFFSET0 0x0A9
|
||||
#define R_BYTEOFFSET1 0x0AA
|
||||
#define R_L2TYPE_0 0x0F0
|
||||
#define O_L2TYPE__ExtraHdrProtoSize 26
|
||||
#define W_L2TYPE__ExtraHdrProtoSize 5
|
||||
#define O_L2TYPE__ExtraHdrProtoOffset 20
|
||||
#define W_L2TYPE__ExtraHdrProtoOffset 6
|
||||
#define O_L2TYPE__ExtraHeaderSize 14
|
||||
#define W_L2TYPE__ExtraHeaderSize 6
|
||||
#define O_L2TYPE__ProtoOffset 8
|
||||
#define W_L2TYPE__ProtoOffset 6
|
||||
#define O_L2TYPE__L2HdrOffset 2
|
||||
#define W_L2TYPE__L2HdrOffset 6
|
||||
#define O_L2TYPE__L2Proto 0
|
||||
#define W_L2TYPE__L2Proto 2
|
||||
#define R_L2TYPE_1 0xF0
|
||||
#define R_L2TYPE_2 0xF0
|
||||
#define R_L2TYPE_3 0xF0
|
||||
#define R_PARSERCONFIGREG 0x100
|
||||
#define O_PARSERCONFIGREG__CRCHashPoly 8
|
||||
#define W_PARSERCONFIGREG__CRCHashPoly 7
|
||||
#define O_PARSERCONFIGREG__PrePadOffset 4
|
||||
#define W_PARSERCONFIGREG__PrePadOffset 4
|
||||
#define O_PARSERCONFIGREG__UseCAM 2
|
||||
#define O_PARSERCONFIGREG__UseHASH 1
|
||||
#define O_PARSERCONFIGREG__UseProto 0
|
||||
#define R_L3CTABLE 0x140
|
||||
#define O_L3CTABLE__Offset0 25
|
||||
#define W_L3CTABLE__Offset0 7
|
||||
#define O_L3CTABLE__Len0 21
|
||||
#define W_L3CTABLE__Len0 4
|
||||
#define O_L3CTABLE__Offset1 14
|
||||
#define W_L3CTABLE__Offset1 7
|
||||
#define O_L3CTABLE__Len1 10
|
||||
#define W_L3CTABLE__Len1 4
|
||||
#define O_L3CTABLE__Offset2 4
|
||||
#define W_L3CTABLE__Offset2 6
|
||||
#define O_L3CTABLE__Len2 0
|
||||
#define W_L3CTABLE__Len2 4
|
||||
#define O_L3CTABLE__L3HdrOffset 26
|
||||
#define W_L3CTABLE__L3HdrOffset 6
|
||||
#define O_L3CTABLE__L4ProtoOffset 20
|
||||
#define W_L3CTABLE__L4ProtoOffset 6
|
||||
#define O_L3CTABLE__IPChksumCompute 19
|
||||
#define O_L3CTABLE__L4Classify 18
|
||||
#define O_L3CTABLE__L2Proto 16
|
||||
#define W_L3CTABLE__L2Proto 2
|
||||
#define O_L3CTABLE__L3ProtoKey 0
|
||||
#define W_L3CTABLE__L3ProtoKey 16
|
||||
#define R_L4CTABLE 0x160
|
||||
#define O_L4CTABLE__Offset0 21
|
||||
#define W_L4CTABLE__Offset0 6
|
||||
#define O_L4CTABLE__Len0 17
|
||||
#define W_L4CTABLE__Len0 4
|
||||
#define O_L4CTABLE__Offset1 11
|
||||
#define W_L4CTABLE__Offset1 6
|
||||
#define O_L4CTABLE__Len1 7
|
||||
#define W_L4CTABLE__Len1 4
|
||||
#define O_L4CTABLE__TCPChksumEnable 0
|
||||
#define R_CAM4X128TABLE 0x172
|
||||
#define O_CAM4X128TABLE__ClassId 7
|
||||
#define W_CAM4X128TABLE__ClassId 2
|
||||
#define O_CAM4X128TABLE__BucketId 1
|
||||
#define W_CAM4X128TABLE__BucketId 6
|
||||
#define O_CAM4X128TABLE__UseBucket 0
|
||||
#define R_CAM4X128KEY 0x180
|
||||
#define R_TRANSLATETABLE 0x1A0
|
||||
#define R_DMACR0 0x200
|
||||
#define O_DMACR0__Data0WrMaxCr 27
|
||||
#define W_DMACR0__Data0WrMaxCr 3
|
||||
#define O_DMACR0__Data0RdMaxCr 24
|
||||
#define W_DMACR0__Data0RdMaxCr 3
|
||||
#define O_DMACR0__Data1WrMaxCr 21
|
||||
#define W_DMACR0__Data1WrMaxCr 3
|
||||
#define O_DMACR0__Data1RdMaxCr 18
|
||||
#define W_DMACR0__Data1RdMaxCr 3
|
||||
#define O_DMACR0__Data2WrMaxCr 15
|
||||
#define W_DMACR0__Data2WrMaxCr 3
|
||||
#define O_DMACR0__Data2RdMaxCr 12
|
||||
#define W_DMACR0__Data2RdMaxCr 3
|
||||
#define O_DMACR0__Data3WrMaxCr 9
|
||||
#define W_DMACR0__Data3WrMaxCr 3
|
||||
#define O_DMACR0__Data3RdMaxCr 6
|
||||
#define W_DMACR0__Data3RdMaxCr 3
|
||||
#define O_DMACR0__Data4WrMaxCr 3
|
||||
#define W_DMACR0__Data4WrMaxCr 3
|
||||
#define O_DMACR0__Data4RdMaxCr 0
|
||||
#define W_DMACR0__Data4RdMaxCr 3
|
||||
#define R_DMACR1 0x201
|
||||
#define O_DMACR1__Data5WrMaxCr 27
|
||||
#define W_DMACR1__Data5WrMaxCr 3
|
||||
#define O_DMACR1__Data5RdMaxCr 24
|
||||
#define W_DMACR1__Data5RdMaxCr 3
|
||||
#define O_DMACR1__Data6WrMaxCr 21
|
||||
#define W_DMACR1__Data6WrMaxCr 3
|
||||
#define O_DMACR1__Data6RdMaxCr 18
|
||||
#define W_DMACR1__Data6RdMaxCr 3
|
||||
#define O_DMACR1__Data7WrMaxCr 15
|
||||
#define W_DMACR1__Data7WrMaxCr 3
|
||||
#define O_DMACR1__Data7RdMaxCr 12
|
||||
#define W_DMACR1__Data7RdMaxCr 3
|
||||
#define O_DMACR1__Data8WrMaxCr 9
|
||||
#define W_DMACR1__Data8WrMaxCr 3
|
||||
#define O_DMACR1__Data8RdMaxCr 6
|
||||
#define W_DMACR1__Data8RdMaxCr 3
|
||||
#define O_DMACR1__Data9WrMaxCr 3
|
||||
#define W_DMACR1__Data9WrMaxCr 3
|
||||
#define O_DMACR1__Data9RdMaxCr 0
|
||||
#define W_DMACR1__Data9RdMaxCr 3
|
||||
#define R_DMACR2 0x202
|
||||
#define O_DMACR2__Data10WrMaxCr 27
|
||||
#define W_DMACR2__Data10WrMaxCr 3
|
||||
#define O_DMACR2__Data10RdMaxCr 24
|
||||
#define W_DMACR2__Data10RdMaxCr 3
|
||||
#define O_DMACR2__Data11WrMaxCr 21
|
||||
#define W_DMACR2__Data11WrMaxCr 3
|
||||
#define O_DMACR2__Data11RdMaxCr 18
|
||||
#define W_DMACR2__Data11RdMaxCr 3
|
||||
#define O_DMACR2__Data12WrMaxCr 15
|
||||
#define W_DMACR2__Data12WrMaxCr 3
|
||||
#define O_DMACR2__Data12RdMaxCr 12
|
||||
#define W_DMACR2__Data12RdMaxCr 3
|
||||
#define O_DMACR2__Data13WrMaxCr 9
|
||||
#define W_DMACR2__Data13WrMaxCr 3
|
||||
#define O_DMACR2__Data13RdMaxCr 6
|
||||
#define W_DMACR2__Data13RdMaxCr 3
|
||||
#define O_DMACR2__Data14WrMaxCr 3
|
||||
#define W_DMACR2__Data14WrMaxCr 3
|
||||
#define O_DMACR2__Data14RdMaxCr 0
|
||||
#define W_DMACR2__Data14RdMaxCr 3
|
||||
#define R_DMACR3 0x203
|
||||
#define O_DMACR3__Data15WrMaxCr 27
|
||||
#define W_DMACR3__Data15WrMaxCr 3
|
||||
#define O_DMACR3__Data15RdMaxCr 24
|
||||
#define W_DMACR3__Data15RdMaxCr 3
|
||||
#define O_DMACR3__SpClassWrMaxCr 21
|
||||
#define W_DMACR3__SpClassWrMaxCr 3
|
||||
#define O_DMACR3__SpClassRdMaxCr 18
|
||||
#define W_DMACR3__SpClassRdMaxCr 3
|
||||
#define O_DMACR3__JumFrInWrMaxCr 15
|
||||
#define W_DMACR3__JumFrInWrMaxCr 3
|
||||
#define O_DMACR3__JumFrInRdMaxCr 12
|
||||
#define W_DMACR3__JumFrInRdMaxCr 3
|
||||
#define O_DMACR3__RegFrInWrMaxCr 9
|
||||
#define W_DMACR3__RegFrInWrMaxCr 3
|
||||
#define O_DMACR3__RegFrInRdMaxCr 6
|
||||
#define W_DMACR3__RegFrInRdMaxCr 3
|
||||
#define O_DMACR3__FrOutWrMaxCr 3
|
||||
#define W_DMACR3__FrOutWrMaxCr 3
|
||||
#define O_DMACR3__FrOutRdMaxCr 0
|
||||
#define W_DMACR3__FrOutRdMaxCr 3
|
||||
#define R_REG_FRIN_SPILL_MEM_START_0 0x204
|
||||
#define O_REG_FRIN_SPILL_MEM_START_0__RegFrInSpillMemStart0 0
|
||||
#define W_REG_FRIN_SPILL_MEM_START_0__RegFrInSpillMemStart0 32
|
||||
#define R_REG_FRIN_SPILL_MEM_START_1 0x205
|
||||
#define O_REG_FRIN_SPILL_MEM_START_1__RegFrInSpillMemStart1 0
|
||||
#define W_REG_FRIN_SPILL_MEM_START_1__RegFrInSpillMemStart1 3
|
||||
#define R_REG_FRIN_SPILL_MEM_SIZE 0x206
|
||||
#define O_REG_FRIN_SPILL_MEM_SIZE__RegFrInSpillMemSize 0
|
||||
#define W_REG_FRIN_SPILL_MEM_SIZE__RegFrInSpillMemSize 32
|
||||
#define R_FROUT_SPILL_MEM_START_0 0x207
|
||||
#define O_FROUT_SPILL_MEM_START_0__FrOutSpillMemStart0 0
|
||||
#define W_FROUT_SPILL_MEM_START_0__FrOutSpillMemStart0 32
|
||||
#define R_FROUT_SPILL_MEM_START_1 0x208
|
||||
#define O_FROUT_SPILL_MEM_START_1__FrOutSpillMemStart1 0
|
||||
#define W_FROUT_SPILL_MEM_START_1__FrOutSpillMemStart1 3
|
||||
#define R_FROUT_SPILL_MEM_SIZE 0x209
|
||||
#define O_FROUT_SPILL_MEM_SIZE__FrOutSpillMemSize 0
|
||||
#define W_FROUT_SPILL_MEM_SIZE__FrOutSpillMemSize 32
|
||||
#define R_CLASS0_SPILL_MEM_START_0 0x20A
|
||||
#define O_CLASS0_SPILL_MEM_START_0__Class0SpillMemStart0 0
|
||||
#define W_CLASS0_SPILL_MEM_START_0__Class0SpillMemStart0 32
|
||||
#define R_CLASS0_SPILL_MEM_START_1 0x20B
|
||||
#define O_CLASS0_SPILL_MEM_START_1__Class0SpillMemStart1 0
|
||||
#define W_CLASS0_SPILL_MEM_START_1__Class0SpillMemStart1 3
|
||||
#define R_CLASS0_SPILL_MEM_SIZE 0x20C
|
||||
#define O_CLASS0_SPILL_MEM_SIZE__Class0SpillMemSize 0
|
||||
#define W_CLASS0_SPILL_MEM_SIZE__Class0SpillMemSize 32
|
||||
#define R_JUMFRIN_SPILL_MEM_START_0 0x20D
|
||||
#define O_JUMFRIN_SPILL_MEM_START_0__JumFrInSpillMemStar0 0
|
||||
#define W_JUMFRIN_SPILL_MEM_START_0__JumFrInSpillMemStar0 32
|
||||
#define R_JUMFRIN_SPILL_MEM_START_1 0x20E
|
||||
#define O_JUMFRIN_SPILL_MEM_START_1__JumFrInSpillMemStart1 0
|
||||
#define W_JUMFRIN_SPILL_MEM_START_1__JumFrInSpillMemStart1 3
|
||||
#define R_JUMFRIN_SPILL_MEM_SIZE 0x20F
|
||||
#define O_JUMFRIN_SPILL_MEM_SIZE__JumFrInSpillMemSize 0
|
||||
#define W_JUMFRIN_SPILL_MEM_SIZE__JumFrInSpillMemSize 32
|
||||
#define R_CLASS1_SPILL_MEM_START_0 0x210
|
||||
#define O_CLASS1_SPILL_MEM_START_0__Class1SpillMemStart0 0
|
||||
#define W_CLASS1_SPILL_MEM_START_0__Class1SpillMemStart0 32
|
||||
#define R_CLASS1_SPILL_MEM_START_1 0x211
|
||||
#define O_CLASS1_SPILL_MEM_START_1__Class1SpillMemStart1 0
|
||||
#define W_CLASS1_SPILL_MEM_START_1__Class1SpillMemStart1 3
|
||||
#define R_CLASS1_SPILL_MEM_SIZE 0x212
|
||||
#define O_CLASS1_SPILL_MEM_SIZE__Class1SpillMemSize 0
|
||||
#define W_CLASS1_SPILL_MEM_SIZE__Class1SpillMemSize 32
|
||||
#define R_CLASS2_SPILL_MEM_START_0 0x213
|
||||
#define O_CLASS2_SPILL_MEM_START_0__Class2SpillMemStart0 0
|
||||
#define W_CLASS2_SPILL_MEM_START_0__Class2SpillMemStart0 32
|
||||
#define R_CLASS2_SPILL_MEM_START_1 0x214
|
||||
#define O_CLASS2_SPILL_MEM_START_1__Class2SpillMemStart1 0
|
||||
#define W_CLASS2_SPILL_MEM_START_1__Class2SpillMemStart1 3
|
||||
#define R_CLASS2_SPILL_MEM_SIZE 0x215
|
||||
#define O_CLASS2_SPILL_MEM_SIZE__Class2SpillMemSize 0
|
||||
#define W_CLASS2_SPILL_MEM_SIZE__Class2SpillMemSize 32
|
||||
#define R_CLASS3_SPILL_MEM_START_0 0x216
|
||||
#define O_CLASS3_SPILL_MEM_START_0__Class3SpillMemStart0 0
|
||||
#define W_CLASS3_SPILL_MEM_START_0__Class3SpillMemStart0 32
|
||||
#define R_CLASS3_SPILL_MEM_START_1 0x217
|
||||
#define O_CLASS3_SPILL_MEM_START_1__Class3SpillMemStart1 0
|
||||
#define W_CLASS3_SPILL_MEM_START_1__Class3SpillMemStart1 3
|
||||
#define R_CLASS3_SPILL_MEM_SIZE 0x218
|
||||
#define O_CLASS3_SPILL_MEM_SIZE__Class3SpillMemSize 0
|
||||
#define W_CLASS3_SPILL_MEM_SIZE__Class3SpillMemSize 32
|
||||
#define R_REG_FRIN1_SPILL_MEM_START_0 0x219
|
||||
#define R_REG_FRIN1_SPILL_MEM_START_1 0x21a
|
||||
#define R_REG_FRIN1_SPILL_MEM_SIZE 0x21b
|
||||
#define R_SPIHNGY0 0x219
|
||||
#define O_SPIHNGY0__EG_HNGY_THRESH_0 24
|
||||
#define W_SPIHNGY0__EG_HNGY_THRESH_0 7
|
||||
#define O_SPIHNGY0__EG_HNGY_THRESH_1 16
|
||||
#define W_SPIHNGY0__EG_HNGY_THRESH_1 7
|
||||
#define O_SPIHNGY0__EG_HNGY_THRESH_2 8
|
||||
#define W_SPIHNGY0__EG_HNGY_THRESH_2 7
|
||||
#define O_SPIHNGY0__EG_HNGY_THRESH_3 0
|
||||
#define W_SPIHNGY0__EG_HNGY_THRESH_3 7
|
||||
#define R_SPIHNGY1 0x21A
|
||||
#define O_SPIHNGY1__EG_HNGY_THRESH_4 24
|
||||
#define W_SPIHNGY1__EG_HNGY_THRESH_4 7
|
||||
#define O_SPIHNGY1__EG_HNGY_THRESH_5 16
|
||||
#define W_SPIHNGY1__EG_HNGY_THRESH_5 7
|
||||
#define O_SPIHNGY1__EG_HNGY_THRESH_6 8
|
||||
#define W_SPIHNGY1__EG_HNGY_THRESH_6 7
|
||||
#define O_SPIHNGY1__EG_HNGY_THRESH_7 0
|
||||
#define W_SPIHNGY1__EG_HNGY_THRESH_7 7
|
||||
#define R_SPIHNGY2 0x21B
|
||||
#define O_SPIHNGY2__EG_HNGY_THRESH_8 24
|
||||
#define W_SPIHNGY2__EG_HNGY_THRESH_8 7
|
||||
#define O_SPIHNGY2__EG_HNGY_THRESH_9 16
|
||||
#define W_SPIHNGY2__EG_HNGY_THRESH_9 7
|
||||
#define O_SPIHNGY2__EG_HNGY_THRESH_10 8
|
||||
#define W_SPIHNGY2__EG_HNGY_THRESH_10 7
|
||||
#define O_SPIHNGY2__EG_HNGY_THRESH_11 0
|
||||
#define W_SPIHNGY2__EG_HNGY_THRESH_11 7
|
||||
#define R_SPIHNGY3 0x21C
|
||||
#define O_SPIHNGY3__EG_HNGY_THRESH_12 24
|
||||
#define W_SPIHNGY3__EG_HNGY_THRESH_12 7
|
||||
#define O_SPIHNGY3__EG_HNGY_THRESH_13 16
|
||||
#define W_SPIHNGY3__EG_HNGY_THRESH_13 7
|
||||
#define O_SPIHNGY3__EG_HNGY_THRESH_14 8
|
||||
#define W_SPIHNGY3__EG_HNGY_THRESH_14 7
|
||||
#define O_SPIHNGY3__EG_HNGY_THRESH_15 0
|
||||
#define W_SPIHNGY3__EG_HNGY_THRESH_15 7
|
||||
#define R_SPISTRV0 0x21D
|
||||
#define O_SPISTRV0__EG_STRV_THRESH_0 24
|
||||
#define W_SPISTRV0__EG_STRV_THRESH_0 7
|
||||
#define O_SPISTRV0__EG_STRV_THRESH_1 16
|
||||
#define W_SPISTRV0__EG_STRV_THRESH_1 7
|
||||
#define O_SPISTRV0__EG_STRV_THRESH_2 8
|
||||
#define W_SPISTRV0__EG_STRV_THRESH_2 7
|
||||
#define O_SPISTRV0__EG_STRV_THRESH_3 0
|
||||
#define W_SPISTRV0__EG_STRV_THRESH_3 7
|
||||
#define R_SPISTRV1 0x21E
|
||||
#define O_SPISTRV1__EG_STRV_THRESH_4 24
|
||||
#define W_SPISTRV1__EG_STRV_THRESH_4 7
|
||||
#define O_SPISTRV1__EG_STRV_THRESH_5 16
|
||||
#define W_SPISTRV1__EG_STRV_THRESH_5 7
|
||||
#define O_SPISTRV1__EG_STRV_THRESH_6 8
|
||||
#define W_SPISTRV1__EG_STRV_THRESH_6 7
|
||||
#define O_SPISTRV1__EG_STRV_THRESH_7 0
|
||||
#define W_SPISTRV1__EG_STRV_THRESH_7 7
|
||||
#define R_SPISTRV2 0x21F
|
||||
#define O_SPISTRV2__EG_STRV_THRESH_8 24
|
||||
#define W_SPISTRV2__EG_STRV_THRESH_8 7
|
||||
#define O_SPISTRV2__EG_STRV_THRESH_9 16
|
||||
#define W_SPISTRV2__EG_STRV_THRESH_9 7
|
||||
#define O_SPISTRV2__EG_STRV_THRESH_10 8
|
||||
#define W_SPISTRV2__EG_STRV_THRESH_10 7
|
||||
#define O_SPISTRV2__EG_STRV_THRESH_11 0
|
||||
#define W_SPISTRV2__EG_STRV_THRESH_11 7
|
||||
#define R_SPISTRV3 0x220
|
||||
#define O_SPISTRV3__EG_STRV_THRESH_12 24
|
||||
#define W_SPISTRV3__EG_STRV_THRESH_12 7
|
||||
#define O_SPISTRV3__EG_STRV_THRESH_13 16
|
||||
#define W_SPISTRV3__EG_STRV_THRESH_13 7
|
||||
#define O_SPISTRV3__EG_STRV_THRESH_14 8
|
||||
#define W_SPISTRV3__EG_STRV_THRESH_14 7
|
||||
#define O_SPISTRV3__EG_STRV_THRESH_15 0
|
||||
#define W_SPISTRV3__EG_STRV_THRESH_15 7
|
||||
#define R_TXDATAFIFO0 0x221
|
||||
#define O_TXDATAFIFO0__Tx0DataFifoStart 24
|
||||
#define W_TXDATAFIFO0__Tx0DataFifoStart 7
|
||||
#define O_TXDATAFIFO0__Tx0DataFifoSize 16
|
||||
#define W_TXDATAFIFO0__Tx0DataFifoSize 7
|
||||
#define O_TXDATAFIFO0__Tx1DataFifoStart 8
|
||||
#define W_TXDATAFIFO0__Tx1DataFifoStart 7
|
||||
#define O_TXDATAFIFO0__Tx1DataFifoSize 0
|
||||
#define W_TXDATAFIFO0__Tx1DataFifoSize 7
|
||||
#define R_TXDATAFIFO1 0x222
|
||||
#define O_TXDATAFIFO1__Tx2DataFifoStart 24
|
||||
#define W_TXDATAFIFO1__Tx2DataFifoStart 7
|
||||
#define O_TXDATAFIFO1__Tx2DataFifoSize 16
|
||||
#define W_TXDATAFIFO1__Tx2DataFifoSize 7
|
||||
#define O_TXDATAFIFO1__Tx3DataFifoStart 8
|
||||
#define W_TXDATAFIFO1__Tx3DataFifoStart 7
|
||||
#define O_TXDATAFIFO1__Tx3DataFifoSize 0
|
||||
#define W_TXDATAFIFO1__Tx3DataFifoSize 7
|
||||
#define R_TXDATAFIFO2 0x223
|
||||
#define O_TXDATAFIFO2__Tx4DataFifoStart 24
|
||||
#define W_TXDATAFIFO2__Tx4DataFifoStart 7
|
||||
#define O_TXDATAFIFO2__Tx4DataFifoSize 16
|
||||
#define W_TXDATAFIFO2__Tx4DataFifoSize 7
|
||||
#define O_TXDATAFIFO2__Tx5DataFifoStart 8
|
||||
#define W_TXDATAFIFO2__Tx5DataFifoStart 7
|
||||
#define O_TXDATAFIFO2__Tx5DataFifoSize 0
|
||||
#define W_TXDATAFIFO2__Tx5DataFifoSize 7
|
||||
#define R_TXDATAFIFO3 0x224
|
||||
#define O_TXDATAFIFO3__Tx6DataFifoStart 24
|
||||
#define W_TXDATAFIFO3__Tx6DataFifoStart 7
|
||||
#define O_TXDATAFIFO3__Tx6DataFifoSize 16
|
||||
#define W_TXDATAFIFO3__Tx6DataFifoSize 7
|
||||
#define O_TXDATAFIFO3__Tx7DataFifoStart 8
|
||||
#define W_TXDATAFIFO3__Tx7DataFifoStart 7
|
||||
#define O_TXDATAFIFO3__Tx7DataFifoSize 0
|
||||
#define W_TXDATAFIFO3__Tx7DataFifoSize 7
|
||||
#define R_TXDATAFIFO4 0x225
|
||||
#define O_TXDATAFIFO4__Tx8DataFifoStart 24
|
||||
#define W_TXDATAFIFO4__Tx8DataFifoStart 7
|
||||
#define O_TXDATAFIFO4__Tx8DataFifoSize 16
|
||||
#define W_TXDATAFIFO4__Tx8DataFifoSize 7
|
||||
#define O_TXDATAFIFO4__Tx9DataFifoStart 8
|
||||
#define W_TXDATAFIFO4__Tx9DataFifoStart 7
|
||||
#define O_TXDATAFIFO4__Tx9DataFifoSize 0
|
||||
#define W_TXDATAFIFO4__Tx9DataFifoSize 7
|
||||
#define R_TXDATAFIFO5 0x226
|
||||
#define O_TXDATAFIFO5__Tx10DataFifoStart 24
|
||||
#define W_TXDATAFIFO5__Tx10DataFifoStart 7
|
||||
#define O_TXDATAFIFO5__Tx10DataFifoSize 16
|
||||
#define W_TXDATAFIFO5__Tx10DataFifoSize 7
|
||||
#define O_TXDATAFIFO5__Tx11DataFifoStart 8
|
||||
#define W_TXDATAFIFO5__Tx11DataFifoStart 7
|
||||
#define O_TXDATAFIFO5__Tx11DataFifoSize 0
|
||||
#define W_TXDATAFIFO5__Tx11DataFifoSize 7
|
||||
#define R_TXDATAFIFO6 0x227
|
||||
#define O_TXDATAFIFO6__Tx12DataFifoStart 24
|
||||
#define W_TXDATAFIFO6__Tx12DataFifoStart 7
|
||||
#define O_TXDATAFIFO6__Tx12DataFifoSize 16
|
||||
#define W_TXDATAFIFO6__Tx12DataFifoSize 7
|
||||
#define O_TXDATAFIFO6__Tx13DataFifoStart 8
|
||||
#define W_TXDATAFIFO6__Tx13DataFifoStart 7
|
||||
#define O_TXDATAFIFO6__Tx13DataFifoSize 0
|
||||
#define W_TXDATAFIFO6__Tx13DataFifoSize 7
|
||||
#define R_TXDATAFIFO7 0x228
|
||||
#define O_TXDATAFIFO7__Tx14DataFifoStart 24
|
||||
#define W_TXDATAFIFO7__Tx14DataFifoStart 7
|
||||
#define O_TXDATAFIFO7__Tx14DataFifoSize 16
|
||||
#define W_TXDATAFIFO7__Tx14DataFifoSize 7
|
||||
#define O_TXDATAFIFO7__Tx15DataFifoStart 8
|
||||
#define W_TXDATAFIFO7__Tx15DataFifoStart 7
|
||||
#define O_TXDATAFIFO7__Tx15DataFifoSize 0
|
||||
#define W_TXDATAFIFO7__Tx15DataFifoSize 7
|
||||
#define R_RXDATAFIFO0 0x229
|
||||
#define O_RXDATAFIFO0__Rx0DataFifoStart 24
|
||||
#define W_RXDATAFIFO0__Rx0DataFifoStart 7
|
||||
#define O_RXDATAFIFO0__Rx0DataFifoSize 16
|
||||
#define W_RXDATAFIFO0__Rx0DataFifoSize 7
|
||||
#define O_RXDATAFIFO0__Rx1DataFifoStart 8
|
||||
#define W_RXDATAFIFO0__Rx1DataFifoStart 7
|
||||
#define O_RXDATAFIFO0__Rx1DataFifoSize 0
|
||||
#define W_RXDATAFIFO0__Rx1DataFifoSize 7
|
||||
#define R_RXDATAFIFO1 0x22A
|
||||
#define O_RXDATAFIFO1__Rx2DataFifoStart 24
|
||||
#define W_RXDATAFIFO1__Rx2DataFifoStart 7
|
||||
#define O_RXDATAFIFO1__Rx2DataFifoSize 16
|
||||
#define W_RXDATAFIFO1__Rx2DataFifoSize 7
|
||||
#define O_RXDATAFIFO1__Rx3DataFifoStart 8
|
||||
#define W_RXDATAFIFO1__Rx3DataFifoStart 7
|
||||
#define O_RXDATAFIFO1__Rx3DataFifoSize 0
|
||||
#define W_RXDATAFIFO1__Rx3DataFifoSize 7
|
||||
#define R_RXDATAFIFO2 0x22B
|
||||
#define O_RXDATAFIFO2__Rx4DataFifoStart 24
|
||||
#define W_RXDATAFIFO2__Rx4DataFifoStart 7
|
||||
#define O_RXDATAFIFO2__Rx4DataFifoSize 16
|
||||
#define W_RXDATAFIFO2__Rx4DataFifoSize 7
|
||||
#define O_RXDATAFIFO2__Rx5DataFifoStart 8
|
||||
#define W_RXDATAFIFO2__Rx5DataFifoStart 7
|
||||
#define O_RXDATAFIFO2__Rx5DataFifoSize 0
|
||||
#define W_RXDATAFIFO2__Rx5DataFifoSize 7
|
||||
#define R_RXDATAFIFO3 0x22C
|
||||
#define O_RXDATAFIFO3__Rx6DataFifoStart 24
|
||||
#define W_RXDATAFIFO3__Rx6DataFifoStart 7
|
||||
#define O_RXDATAFIFO3__Rx6DataFifoSize 16
|
||||
#define W_RXDATAFIFO3__Rx6DataFifoSize 7
|
||||
#define O_RXDATAFIFO3__Rx7DataFifoStart 8
|
||||
#define W_RXDATAFIFO3__Rx7DataFifoStart 7
|
||||
#define O_RXDATAFIFO3__Rx7DataFifoSize 0
|
||||
#define W_RXDATAFIFO3__Rx7DataFifoSize 7
|
||||
#define R_RXDATAFIFO4 0x22D
|
||||
#define O_RXDATAFIFO4__Rx8DataFifoStart 24
|
||||
#define W_RXDATAFIFO4__Rx8DataFifoStart 7
|
||||
#define O_RXDATAFIFO4__Rx8DataFifoSize 16
|
||||
#define W_RXDATAFIFO4__Rx8DataFifoSize 7
|
||||
#define O_RXDATAFIFO4__Rx9DataFifoStart 8
|
||||
#define W_RXDATAFIFO4__Rx9DataFifoStart 7
|
||||
#define O_RXDATAFIFO4__Rx9DataFifoSize 0
|
||||
#define W_RXDATAFIFO4__Rx9DataFifoSize 7
|
||||
#define R_RXDATAFIFO5 0x22E
|
||||
#define O_RXDATAFIFO5__Rx10DataFifoStart 24
|
||||
#define W_RXDATAFIFO5__Rx10DataFifoStart 7
|
||||
#define O_RXDATAFIFO5__Rx10DataFifoSize 16
|
||||
#define W_RXDATAFIFO5__Rx10DataFifoSize 7
|
||||
#define O_RXDATAFIFO5__Rx11DataFifoStart 8
|
||||
#define W_RXDATAFIFO5__Rx11DataFifoStart 7
|
||||
#define O_RXDATAFIFO5__Rx11DataFifoSize 0
|
||||
#define W_RXDATAFIFO5__Rx11DataFifoSize 7
|
||||
#define R_RXDATAFIFO6 0x22F
|
||||
#define O_RXDATAFIFO6__Rx12DataFifoStart 24
|
||||
#define W_RXDATAFIFO6__Rx12DataFifoStart 7
|
||||
#define O_RXDATAFIFO6__Rx12DataFifoSize 16
|
||||
#define W_RXDATAFIFO6__Rx12DataFifoSize 7
|
||||
#define O_RXDATAFIFO6__Rx13DataFifoStart 8
|
||||
#define W_RXDATAFIFO6__Rx13DataFifoStart 7
|
||||
#define O_RXDATAFIFO6__Rx13DataFifoSize 0
|
||||
#define W_RXDATAFIFO6__Rx13DataFifoSize 7
|
||||
#define R_RXDATAFIFO7 0x230
|
||||
#define O_RXDATAFIFO7__Rx14DataFifoStart 24
|
||||
#define W_RXDATAFIFO7__Rx14DataFifoStart 7
|
||||
#define O_RXDATAFIFO7__Rx14DataFifoSize 16
|
||||
#define W_RXDATAFIFO7__Rx14DataFifoSize 7
|
||||
#define O_RXDATAFIFO7__Rx15DataFifoStart 8
|
||||
#define W_RXDATAFIFO7__Rx15DataFifoStart 7
|
||||
#define O_RXDATAFIFO7__Rx15DataFifoSize 0
|
||||
#define W_RXDATAFIFO7__Rx15DataFifoSize 7
|
||||
#define R_XGMACPADCALIBRATION 0x231
|
||||
#define R_FREEQCARVE 0x233
|
||||
#define R_SPI4STATICDELAY0 0x240
|
||||
#define O_SPI4STATICDELAY0__DataLine7 28
|
||||
#define W_SPI4STATICDELAY0__DataLine7 4
|
||||
#define O_SPI4STATICDELAY0__DataLine6 24
|
||||
#define W_SPI4STATICDELAY0__DataLine6 4
|
||||
#define O_SPI4STATICDELAY0__DataLine5 20
|
||||
#define W_SPI4STATICDELAY0__DataLine5 4
|
||||
#define O_SPI4STATICDELAY0__DataLine4 16
|
||||
#define W_SPI4STATICDELAY0__DataLine4 4
|
||||
#define O_SPI4STATICDELAY0__DataLine3 12
|
||||
#define W_SPI4STATICDELAY0__DataLine3 4
|
||||
#define O_SPI4STATICDELAY0__DataLine2 8
|
||||
#define W_SPI4STATICDELAY0__DataLine2 4
|
||||
#define O_SPI4STATICDELAY0__DataLine1 4
|
||||
#define W_SPI4STATICDELAY0__DataLine1 4
|
||||
#define O_SPI4STATICDELAY0__DataLine0 0
|
||||
#define W_SPI4STATICDELAY0__DataLine0 4
|
||||
#define R_SPI4STATICDELAY1 0x241
|
||||
#define O_SPI4STATICDELAY1__DataLine15 28
|
||||
#define W_SPI4STATICDELAY1__DataLine15 4
|
||||
#define O_SPI4STATICDELAY1__DataLine14 24
|
||||
#define W_SPI4STATICDELAY1__DataLine14 4
|
||||
#define O_SPI4STATICDELAY1__DataLine13 20
|
||||
#define W_SPI4STATICDELAY1__DataLine13 4
|
||||
#define O_SPI4STATICDELAY1__DataLine12 16
|
||||
#define W_SPI4STATICDELAY1__DataLine12 4
|
||||
#define O_SPI4STATICDELAY1__DataLine11 12
|
||||
#define W_SPI4STATICDELAY1__DataLine11 4
|
||||
#define O_SPI4STATICDELAY1__DataLine10 8
|
||||
#define W_SPI4STATICDELAY1__DataLine10 4
|
||||
#define O_SPI4STATICDELAY1__DataLine9 4
|
||||
#define W_SPI4STATICDELAY1__DataLine9 4
|
||||
#define O_SPI4STATICDELAY1__DataLine8 0
|
||||
#define W_SPI4STATICDELAY1__DataLine8 4
|
||||
#define R_SPI4STATICDELAY2 0x242
|
||||
#define O_SPI4STATICDELAY0__TxStat1 8
|
||||
#define W_SPI4STATICDELAY0__TxStat1 4
|
||||
#define O_SPI4STATICDELAY0__TxStat0 4
|
||||
#define W_SPI4STATICDELAY0__TxStat0 4
|
||||
#define O_SPI4STATICDELAY0__RxControl 0
|
||||
#define W_SPI4STATICDELAY0__RxControl 4
|
||||
#define R_SPI4CONTROL 0x243
|
||||
#define O_SPI4CONTROL__StaticDelay 2
|
||||
#define O_SPI4CONTROL__LVDS_LVTTL 1
|
||||
#define O_SPI4CONTROL__SPI4Enable 0
|
||||
#define R_CLASSWATERMARKS 0x244
|
||||
#define O_CLASSWATERMARKS__Class0Watermark 24
|
||||
#define W_CLASSWATERMARKS__Class0Watermark 5
|
||||
#define O_CLASSWATERMARKS__Class1Watermark 16
|
||||
#define W_CLASSWATERMARKS__Class1Watermark 5
|
||||
#define O_CLASSWATERMARKS__Class3Watermark 0
|
||||
#define W_CLASSWATERMARKS__Class3Watermark 5
|
||||
#define R_RXWATERMARKS1 0x245
|
||||
#define O_RXWATERMARKS__Rx0DataWatermark 24
|
||||
#define W_RXWATERMARKS__Rx0DataWatermark 7
|
||||
#define O_RXWATERMARKS__Rx1DataWatermark 16
|
||||
#define W_RXWATERMARKS__Rx1DataWatermark 7
|
||||
#define O_RXWATERMARKS__Rx3DataWatermark 0
|
||||
#define W_RXWATERMARKS__Rx3DataWatermark 7
|
||||
#define R_RXWATERMARKS2 0x246
|
||||
#define O_RXWATERMARKS__Rx4DataWatermark 24
|
||||
#define W_RXWATERMARKS__Rx4DataWatermark 7
|
||||
#define O_RXWATERMARKS__Rx5DataWatermark 16
|
||||
#define W_RXWATERMARKS__Rx5DataWatermark 7
|
||||
#define O_RXWATERMARKS__Rx6DataWatermark 8
|
||||
#define W_RXWATERMARKS__Rx6DataWatermark 7
|
||||
#define O_RXWATERMARKS__Rx7DataWatermark 0
|
||||
#define W_RXWATERMARKS__Rx7DataWatermark 7
|
||||
#define R_RXWATERMARKS3 0x247
|
||||
#define O_RXWATERMARKS__Rx8DataWatermark 24
|
||||
#define W_RXWATERMARKS__Rx8DataWatermark 7
|
||||
#define O_RXWATERMARKS__Rx9DataWatermark 16
|
||||
#define W_RXWATERMARKS__Rx9DataWatermark 7
|
||||
#define O_RXWATERMARKS__Rx10DataWatermark 8
|
||||
#define W_RXWATERMARKS__Rx10DataWatermark 7
|
||||
#define O_RXWATERMARKS__Rx11DataWatermark 0
|
||||
#define W_RXWATERMARKS__Rx11DataWatermark 7
|
||||
#define R_RXWATERMARKS4 0x248
|
||||
#define O_RXWATERMARKS__Rx12DataWatermark 24
|
||||
#define W_RXWATERMARKS__Rx12DataWatermark 7
|
||||
#define O_RXWATERMARKS__Rx13DataWatermark 16
|
||||
#define W_RXWATERMARKS__Rx13DataWatermark 7
|
||||
#define O_RXWATERMARKS__Rx14DataWatermark 8
|
||||
#define W_RXWATERMARKS__Rx14DataWatermark 7
|
||||
#define O_RXWATERMARKS__Rx15DataWatermark 0
|
||||
#define W_RXWATERMARKS__Rx15DataWatermark 7
|
||||
#define R_FREEWATERMARKS 0x249
|
||||
#define O_FREEWATERMARKS__FreeOutWatermark 16
|
||||
#define W_FREEWATERMARKS__FreeOutWatermark 16
|
||||
#define O_FREEWATERMARKS__JumFrWatermark 8
|
||||
#define W_FREEWATERMARKS__JumFrWatermark 7
|
||||
#define O_FREEWATERMARKS__RegFrWatermark 0
|
||||
#define W_FREEWATERMARKS__RegFrWatermark 7
|
||||
#define R_EGRESSFIFOCARVINGSLOTS 0x24a
|
||||
|
||||
#define CTRL_RES0 0
|
||||
#define CTRL_RES1 1
|
||||
#define CTRL_REG_FREE 2
|
||||
#define CTRL_JUMBO_FREE 3
|
||||
#define CTRL_CONT 4
|
||||
#define CTRL_EOP 5
|
||||
#define CTRL_START 6
|
||||
#define CTRL_SNGL 7
|
||||
|
||||
#define CTRL_B0_NOT_EOP 0
|
||||
#define CTRL_B0_EOP 1
|
||||
|
||||
#define R_ROUND_ROBIN_TABLE 0
|
||||
#define R_PDE_CLASS_0 0x300
|
||||
#define R_PDE_CLASS_1 0x302
|
||||
#define R_PDE_CLASS_2 0x304
|
||||
#define R_PDE_CLASS_3 0x306
|
||||
|
||||
#define R_MSG_TX_THRESHOLD 0x308
|
||||
|
||||
#define R_GMAC_JFR0_BUCKET_SIZE 0x320
|
||||
#define R_GMAC_RFR0_BUCKET_SIZE 0x321
|
||||
#define R_GMAC_TX0_BUCKET_SIZE 0x322
|
||||
#define R_GMAC_TX1_BUCKET_SIZE 0x323
|
||||
#define R_GMAC_TX2_BUCKET_SIZE 0x324
|
||||
#define R_GMAC_TX3_BUCKET_SIZE 0x325
|
||||
#define R_GMAC_JFR1_BUCKET_SIZE 0x326
|
||||
#define R_GMAC_RFR1_BUCKET_SIZE 0x327
|
||||
|
||||
#define R_XGS_TX0_BUCKET_SIZE 0x320
|
||||
#define R_XGS_TX1_BUCKET_SIZE 0x321
|
||||
#define R_XGS_TX2_BUCKET_SIZE 0x322
|
||||
#define R_XGS_TX3_BUCKET_SIZE 0x323
|
||||
#define R_XGS_TX4_BUCKET_SIZE 0x324
|
||||
#define R_XGS_TX5_BUCKET_SIZE 0x325
|
||||
#define R_XGS_TX6_BUCKET_SIZE 0x326
|
||||
#define R_XGS_TX7_BUCKET_SIZE 0x327
|
||||
#define R_XGS_TX8_BUCKET_SIZE 0x328
|
||||
#define R_XGS_TX9_BUCKET_SIZE 0x329
|
||||
#define R_XGS_TX10_BUCKET_SIZE 0x32A
|
||||
#define R_XGS_TX11_BUCKET_SIZE 0x32B
|
||||
#define R_XGS_TX12_BUCKET_SIZE 0x32C
|
||||
#define R_XGS_TX13_BUCKET_SIZE 0x32D
|
||||
#define R_XGS_TX14_BUCKET_SIZE 0x32E
|
||||
#define R_XGS_TX15_BUCKET_SIZE 0x32F
|
||||
#define R_XGS_JFR_BUCKET_SIZE 0x330
|
||||
#define R_XGS_RFR_BUCKET_SIZE 0x331
|
||||
|
||||
#define R_CC_CPU0_0 0x380
|
||||
#define R_CC_CPU1_0 0x388
|
||||
#define R_CC_CPU2_0 0x390
|
||||
#define R_CC_CPU3_0 0x398
|
||||
#define R_CC_CPU4_0 0x3a0
|
||||
#define R_CC_CPU5_0 0x3a8
|
||||
#define R_CC_CPU6_0 0x3b0
|
||||
#define R_CC_CPU7_0 0x3b8
|
||||
|
||||
struct size_1_desc {
|
||||
uint64_t entry0;
|
||||
};
|
||||
|
||||
struct size_2_desc {
|
||||
uint64_t entry0;
|
||||
uint64_t entry1;
|
||||
};
|
||||
|
||||
struct size_3_desc {
|
||||
uint64_t entry0;
|
||||
uint64_t entry1;
|
||||
uint64_t entry2;
|
||||
};
|
||||
|
||||
struct size_4_desc {
|
||||
uint64_t entry0;
|
||||
uint64_t entry1;
|
||||
uint64_t entry2;
|
||||
uint64_t entry3;
|
||||
};
|
||||
|
||||
struct fr_desc {
|
||||
struct size_1_desc d1;
|
||||
};
|
||||
|
||||
union rx_tx_desc {
|
||||
struct size_2_desc d2;
|
||||
/* struct size_3_desc d3; */
|
||||
/* struct size_4_desc d4; */
|
||||
};
|
||||
|
||||
|
||||
extern unsigned char xlr_base_mac_addr[];
|
||||
|
||||
#endif
|
||||
127
sys/dev/rmi/xlr/xgmac_mdio.h
Normal file
127
sys/dev/rmi/xlr/xgmac_mdio.h
Normal file
|
|
@ -0,0 +1,127 @@
|
|||
/*-
|
||||
* Copyright (c) 2003-2009 RMI Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of RMI Corporation, nor the names of its contributors,
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* RMI_BSD */
|
||||
/* MDIO Low level Access routines */
|
||||
/* All Phy's accessed from GMAC0 base */
|
||||
|
||||
#ifndef _XGMAC_MDIO_H_
|
||||
#define _XGMAC_MDIO_H_
|
||||
|
||||
static inline int
|
||||
xmdio_read(volatile unsigned int *_mmio,
|
||||
uint32_t phy_addr, uint32_t address);
|
||||
static inline void
|
||||
xmdio_write(volatile unsigned int *_mmio,
|
||||
uint32_t phy_addr, uint32_t address, uint32_t data);
|
||||
static inline void
|
||||
xmdio_address(volatile unsigned int *_mmio,
|
||||
uint32_t phy_addr, uint32_t dev_ad, uint32_t address);
|
||||
|
||||
static inline void
|
||||
xmdio_address(volatile unsigned int *_mmio,
|
||||
uint32_t phy_addr, uint32_t dev_ad, uint32_t address)
|
||||
{
|
||||
uint32_t st_field = 0x0;
|
||||
uint32_t op_type = 0x0; /* address operation */
|
||||
uint32_t ta_field = 0x2; /* ta field */
|
||||
|
||||
_mmio[0x11] = ((st_field & 0x3) << 30) |
|
||||
((op_type & 0x3) << 28) |
|
||||
((phy_addr & 0x1F) << 23) |
|
||||
((dev_ad & 0x1F) << 18) |
|
||||
((ta_field & 0x3) << 16) |
|
||||
((address & 0xffff) << 0);
|
||||
|
||||
_mmio[0x10] = (0x0 << 3) | 0x5;
|
||||
_mmio[0x10] = (0x1 << 3) | 0x5;
|
||||
_mmio[0x10] = (0x0 << 3) | 0x5;
|
||||
|
||||
/* wait for dev_ad cycle to complete */
|
||||
while (_mmio[0x14] & 0x1) {
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
/* function prototypes */
|
||||
static inline int
|
||||
xmdio_read(volatile unsigned int *_mmio,
|
||||
uint32_t phy_addr, uint32_t address)
|
||||
{
|
||||
uint32_t st_field = 0x0;
|
||||
uint32_t op_type = 0x3; /* read operation */
|
||||
uint32_t ta_field = 0x2; /* ta field */
|
||||
uint32_t data = 0;
|
||||
|
||||
xmdio_address(_mmio, phy_addr, 5, address);
|
||||
_mmio[0x11] = ((st_field & 0x3) << 30) |
|
||||
((op_type & 0x3) << 28) |
|
||||
((phy_addr & 0x1F) << 23) |
|
||||
((5 & 0x1F) << 18) |
|
||||
((ta_field & 0x3) << 16) |
|
||||
((data & 0xffff) << 0);
|
||||
|
||||
_mmio[0x10] = (0x0 << 3) | 0x5;
|
||||
_mmio[0x10] = (0x1 << 3) | 0x5;
|
||||
_mmio[0x10] = (0x0 << 3) | 0x5;
|
||||
|
||||
/* wait for write cycle to complete */
|
||||
while (_mmio[0x14] & 0x1) {
|
||||
};
|
||||
|
||||
data = _mmio[0x11] & 0xffff;
|
||||
return (data);
|
||||
}
|
||||
|
||||
static inline void
|
||||
xmdio_write(volatile unsigned int *_mmio,
|
||||
uint32_t phy_addr, uint32_t address, uint32_t data)
|
||||
{
|
||||
uint32_t st_field = 0x0;
|
||||
uint32_t op_type = 0x1; /* write operation */
|
||||
uint32_t ta_field = 0x2; /* ta field */
|
||||
|
||||
xmdio_address(_mmio, phy_addr, 5, address);
|
||||
_mmio[0x11] = ((st_field & 0x3) << 30) |
|
||||
((op_type & 0x3) << 28) |
|
||||
((phy_addr & 0x1F) << 23) |
|
||||
((5 & 0x1F) << 18) |
|
||||
((ta_field & 0x3) << 16) |
|
||||
((data & 0xffff) << 0);
|
||||
|
||||
_mmio[0x10] = (0x0 << 3) | 0x5;
|
||||
_mmio[0x10] = (0x1 << 3) | 0x5;
|
||||
_mmio[0x10] = (0x0 << 3) | 0x5;
|
||||
|
||||
/* wait for write cycle to complete */
|
||||
while (_mmio[0x14] & 0x1) {
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue