2010-01-01 05:31:22 -05:00
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//===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the X86 Disassembler Emitter.
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// It contains the implementation of a single recognizable instruction.
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// Documentation for the disassembler emitter in general can be found in
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2017-07-13 15:25:18 -04:00
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// X86DisassemblerEmitter.h.
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2010-01-01 05:31:22 -05:00
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//
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//===----------------------------------------------------------------------===//
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#include "X86RecognizableInstr.h"
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2013-04-08 14:41:23 -04:00
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#include "X86DisassemblerShared.h"
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2010-01-01 05:31:22 -05:00
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#include "X86ModRMFilters.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <string>
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using namespace llvm;
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2014-11-24 04:08:18 -05:00
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using namespace X86Disassembler;
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2010-01-01 05:31:22 -05:00
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/// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
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/// Useful for switch statements and the like.
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///
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/// @param init - A reference to the BitsInit to be decoded.
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/// @return - The field, with the first bit in the BitsInit as the lowest
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/// order bit.
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static uint8_t byteFromBitsInit(BitsInit &init) {
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int width = init.getNumBits();
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assert(width <= 8 && "Field is too large for uint8_t!");
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int index;
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uint8_t mask = 0x01;
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uint8_t ret = 0;
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for (index = 0; index < width; index++) {
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2018-07-28 06:51:19 -04:00
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if (cast<BitInit>(init.getBit(index))->getValue())
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2010-01-01 05:31:22 -05:00
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ret |= mask;
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mask <<= 1;
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}
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return ret;
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}
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/// byteFromRec - Extract a value at most 8 bits in with from a Record given the
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/// name of the field.
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///
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/// @param rec - The record from which to extract the value.
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/// @param name - The name of the field in the record.
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/// @return - The field, as translated by byteFromBitsInit().
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static uint8_t byteFromRec(const Record* rec, const std::string &name) {
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BitsInit* bits = rec->getValueAsBitsInit(name);
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return byteFromBitsInit(*bits);
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}
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RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
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const CodeGenInstruction &insn,
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InstrUID uid) {
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UID = uid;
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Rec = insn.TheDef;
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Name = Rec->getName();
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Spec = &tables.specForUID(UID);
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2012-08-15 15:34:23 -04:00
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2010-01-01 05:31:22 -05:00
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if (!Rec->isSubClassOf("X86Inst")) {
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ShouldBeEmitted = false;
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return;
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}
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2012-08-15 15:34:23 -04:00
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2014-11-24 04:08:18 -05:00
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OpPrefix = byteFromRec(Rec, "OpPrefixBits");
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OpMap = byteFromRec(Rec, "OpMapBits");
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2010-01-01 05:31:22 -05:00
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Opcode = byteFromRec(Rec, "Opcode");
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Form = byteFromRec(Rec, "FormBits");
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2014-11-24 04:08:18 -05:00
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Encoding = byteFromRec(Rec, "OpEncBits");
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2012-08-15 15:34:23 -04:00
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2018-07-28 06:51:19 -04:00
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OpSize = byteFromRec(Rec, "OpSizeBits");
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AdSize = byteFromRec(Rec, "AdSizeBits");
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HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
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HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
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VEX_WPrefix = byteFromRec(Rec,"VEX_WPrefix");
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IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
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HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
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HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
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HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
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HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
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IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
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ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
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CD8_Scale = byteFromRec(Rec, "CD8_Scale");
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2012-08-15 15:34:23 -04:00
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2010-01-01 05:31:22 -05:00
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Name = Rec->getName();
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2012-08-15 15:34:23 -04:00
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2011-02-20 07:57:14 -05:00
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Operands = &insn.Operands.OperandList;
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2012-08-15 15:34:23 -04:00
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2012-12-02 08:10:19 -05:00
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HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
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2012-04-14 09:54:10 -04:00
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2017-12-18 15:10:56 -05:00
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EncodeRC = HasEVEX_B &&
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(Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg);
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2011-07-17 11:36:56 -04:00
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// Check for 64-bit inst which does not require REX
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2011-10-20 17:10:27 -04:00
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Is32Bit = false;
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2011-07-17 11:36:56 -04:00
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Is64Bit = false;
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// FIXME: Is there some better way to check for In64BitMode?
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std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
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for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
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2014-11-24 04:08:18 -05:00
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if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
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Predicates[i]->getName().find("In32Bit") != Name.npos) {
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2011-10-20 17:10:27 -04:00
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Is32Bit = true;
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break;
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}
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2014-11-24 04:08:18 -05:00
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if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
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2011-07-17 11:36:56 -04:00
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Is64Bit = true;
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break;
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}
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}
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2014-11-24 04:08:18 -05:00
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if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) {
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ShouldBeEmitted = false;
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return;
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}
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// Special case since there is no attribute class for 64-bit and VEX
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if (Name == "VMASKMOVDQU64") {
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ShouldBeEmitted = false;
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return;
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}
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2011-07-17 11:36:56 -04:00
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2010-01-01 05:31:22 -05:00
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ShouldBeEmitted = true;
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}
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2012-08-15 15:34:23 -04:00
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2010-01-01 05:31:22 -05:00
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void RecognizableInstr::processInstr(DisassemblerTables &tables,
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2012-08-15 15:34:23 -04:00
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const CodeGenInstruction &insn,
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InstrUID uid)
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2010-01-01 05:31:22 -05:00
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{
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2010-05-27 11:15:58 -04:00
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// Ignore "asm parser only" instructions.
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if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
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return;
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2012-08-15 15:34:23 -04:00
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2010-01-01 05:31:22 -05:00
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RecognizableInstr recogInstr(tables, insn, uid);
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2012-08-15 15:34:23 -04:00
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2014-11-24 04:08:18 -05:00
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if (recogInstr.shouldBeEmitted()) {
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recogInstr.emitInstructionSpecifier();
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2010-01-01 05:31:22 -05:00
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recogInstr.emitDecodePath(tables);
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2014-11-24 04:08:18 -05:00
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}
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2010-01-01 05:31:22 -05:00
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}
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2013-12-21 19:04:03 -05:00
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#define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
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(HasEVEX_K && HasEVEX_B ? n##_K_B : \
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(HasEVEX_KZ ? n##_KZ : \
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(HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
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2010-01-01 05:31:22 -05:00
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InstructionContext RecognizableInstr::insnContext() const {
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InstructionContext insnContext;
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2014-11-24 04:08:18 -05:00
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if (Encoding == X86Local::EVEX) {
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2013-12-21 19:04:03 -05:00
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if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
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errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
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llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
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}
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// VEX_L & VEX_W
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2018-07-28 06:51:19 -04:00
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if (!EncodeRC && HasVEX_LPrefix && (VEX_WPrefix == X86Local::VEX_W1 ||
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VEX_WPrefix == X86Local::VEX_W1X)) {
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2014-11-24 04:08:18 -05:00
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if (OpPrefix == X86Local::PD)
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2013-12-21 19:04:03 -05:00
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insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
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2014-11-24 04:08:18 -05:00
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else if (OpPrefix == X86Local::XS)
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2013-12-21 19:04:03 -05:00
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insnContext = EVEX_KB(IC_EVEX_L_W_XS);
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2014-11-24 04:08:18 -05:00
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else if (OpPrefix == X86Local::XD)
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2013-12-21 19:04:03 -05:00
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insnContext = EVEX_KB(IC_EVEX_L_W_XD);
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2014-11-24 04:08:18 -05:00
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else if (OpPrefix == X86Local::PS)
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2013-12-21 19:04:03 -05:00
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insnContext = EVEX_KB(IC_EVEX_L_W);
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2014-11-24 04:08:18 -05:00
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else {
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errs() << "Instruction does not use a prefix: " << Name << "\n";
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llvm_unreachable("Invalid prefix");
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}
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2017-12-18 15:10:56 -05:00
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} else if (!EncodeRC && HasVEX_LPrefix) {
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2013-12-21 19:04:03 -05:00
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// VEX_L
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2014-11-24 04:08:18 -05:00
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if (OpPrefix == X86Local::PD)
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2013-12-21 19:04:03 -05:00
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insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
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2014-11-24 04:08:18 -05:00
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else if (OpPrefix == X86Local::XS)
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2013-12-21 19:04:03 -05:00
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insnContext = EVEX_KB(IC_EVEX_L_XS);
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2014-11-24 04:08:18 -05:00
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else if (OpPrefix == X86Local::XD)
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2013-12-21 19:04:03 -05:00
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insnContext = EVEX_KB(IC_EVEX_L_XD);
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2014-11-24 04:08:18 -05:00
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else if (OpPrefix == X86Local::PS)
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2013-12-21 19:04:03 -05:00
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insnContext = EVEX_KB(IC_EVEX_L);
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2014-11-24 04:08:18 -05:00
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else {
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errs() << "Instruction does not use a prefix: " << Name << "\n";
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llvm_unreachable("Invalid prefix");
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}
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2017-12-18 15:10:56 -05:00
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} else if (!EncodeRC && HasEVEX_L2Prefix &&
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2018-07-28 06:51:19 -04:00
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(VEX_WPrefix == X86Local::VEX_W1 ||
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VEX_WPrefix == X86Local::VEX_W1X)) {
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2013-12-21 19:04:03 -05:00
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// EVEX_L2 & VEX_W
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2014-11-24 04:08:18 -05:00
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if (OpPrefix == X86Local::PD)
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2013-12-21 19:04:03 -05:00
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insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
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2014-11-24 04:08:18 -05:00
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else if (OpPrefix == X86Local::XS)
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2013-12-21 19:04:03 -05:00
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insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
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2014-11-24 04:08:18 -05:00
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else if (OpPrefix == X86Local::XD)
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2013-12-21 19:04:03 -05:00
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insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
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2014-11-24 04:08:18 -05:00
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else if (OpPrefix == X86Local::PS)
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2013-12-21 19:04:03 -05:00
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insnContext = EVEX_KB(IC_EVEX_L2_W);
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2014-11-24 04:08:18 -05:00
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else {
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errs() << "Instruction does not use a prefix: " << Name << "\n";
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llvm_unreachable("Invalid prefix");
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}
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2017-12-18 15:10:56 -05:00
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} else if (!EncodeRC && HasEVEX_L2Prefix) {
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2013-12-21 19:04:03 -05:00
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// EVEX_L2
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2014-11-24 04:08:18 -05:00
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if (OpPrefix == X86Local::PD)
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2013-12-21 19:04:03 -05:00
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insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
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2014-11-24 04:08:18 -05:00
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else if (OpPrefix == X86Local::XD)
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2013-12-21 19:04:03 -05:00
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insnContext = EVEX_KB(IC_EVEX_L2_XD);
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2014-11-24 04:08:18 -05:00
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else if (OpPrefix == X86Local::XS)
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2013-12-21 19:04:03 -05:00
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insnContext = EVEX_KB(IC_EVEX_L2_XS);
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2014-11-24 04:08:18 -05:00
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else if (OpPrefix == X86Local::PS)
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2013-12-21 19:04:03 -05:00
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insnContext = EVEX_KB(IC_EVEX_L2);
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2014-11-24 04:08:18 -05:00
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else {
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errs() << "Instruction does not use a prefix: " << Name << "\n";
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llvm_unreachable("Invalid prefix");
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}
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2013-12-21 19:04:03 -05:00
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}
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2018-07-28 06:51:19 -04:00
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else if (VEX_WPrefix == X86Local::VEX_W1 ||
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VEX_WPrefix == X86Local::VEX_W1X) {
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2013-12-21 19:04:03 -05:00
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// VEX_W
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2014-11-24 04:08:18 -05:00
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if (OpPrefix == X86Local::PD)
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2013-12-21 19:04:03 -05:00
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insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
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2014-11-24 04:08:18 -05:00
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else if (OpPrefix == X86Local::XS)
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2013-12-21 19:04:03 -05:00
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insnContext = EVEX_KB(IC_EVEX_W_XS);
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2014-11-24 04:08:18 -05:00
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else if (OpPrefix == X86Local::XD)
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2013-12-21 19:04:03 -05:00
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insnContext = EVEX_KB(IC_EVEX_W_XD);
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2014-11-24 04:08:18 -05:00
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else if (OpPrefix == X86Local::PS)
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2013-12-21 19:04:03 -05:00
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insnContext = EVEX_KB(IC_EVEX_W);
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2014-11-24 04:08:18 -05:00
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else {
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errs() << "Instruction does not use a prefix: " << Name << "\n";
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llvm_unreachable("Invalid prefix");
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}
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2013-12-21 19:04:03 -05:00
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}
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// No L, no W
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2014-11-24 04:08:18 -05:00
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else if (OpPrefix == X86Local::PD)
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2013-12-21 19:04:03 -05:00
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insnContext = EVEX_KB(IC_EVEX_OPSIZE);
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2014-11-24 04:08:18 -05:00
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else if (OpPrefix == X86Local::XD)
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2013-12-21 19:04:03 -05:00
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insnContext = EVEX_KB(IC_EVEX_XD);
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2014-11-24 04:08:18 -05:00
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else if (OpPrefix == X86Local::XS)
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2013-12-21 19:04:03 -05:00
|
|
|
insnContext = EVEX_KB(IC_EVEX_XS);
|
2018-07-28 06:51:19 -04:00
|
|
|
else if (OpPrefix == X86Local::PS)
|
2013-12-21 19:04:03 -05:00
|
|
|
insnContext = EVEX_KB(IC_EVEX);
|
2018-07-28 06:51:19 -04:00
|
|
|
else {
|
|
|
|
|
errs() << "Instruction does not use a prefix: " << Name << "\n";
|
|
|
|
|
llvm_unreachable("Invalid prefix");
|
|
|
|
|
}
|
2013-12-21 19:04:03 -05:00
|
|
|
/// eof EVEX
|
2014-11-24 04:08:18 -05:00
|
|
|
} else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) {
|
2018-07-28 06:51:19 -04:00
|
|
|
if (HasVEX_LPrefix && (VEX_WPrefix == X86Local::VEX_W1 ||
|
|
|
|
|
VEX_WPrefix == X86Local::VEX_W1X)) {
|
2014-11-24 04:08:18 -05:00
|
|
|
if (OpPrefix == X86Local::PD)
|
2012-04-14 09:54:10 -04:00
|
|
|
insnContext = IC_VEX_L_W_OPSIZE;
|
2014-11-24 04:08:18 -05:00
|
|
|
else if (OpPrefix == X86Local::XS)
|
2013-12-21 19:04:03 -05:00
|
|
|
insnContext = IC_VEX_L_W_XS;
|
2014-11-24 04:08:18 -05:00
|
|
|
else if (OpPrefix == X86Local::XD)
|
2013-12-21 19:04:03 -05:00
|
|
|
insnContext = IC_VEX_L_W_XD;
|
2014-11-24 04:08:18 -05:00
|
|
|
else if (OpPrefix == X86Local::PS)
|
2013-12-21 19:04:03 -05:00
|
|
|
insnContext = IC_VEX_L_W;
|
2014-11-24 04:08:18 -05:00
|
|
|
else {
|
|
|
|
|
errs() << "Instruction does not use a prefix: " << Name << "\n";
|
|
|
|
|
llvm_unreachable("Invalid prefix");
|
|
|
|
|
}
|
|
|
|
|
} else if (OpPrefix == X86Local::PD && HasVEX_LPrefix)
|
2011-05-02 15:34:44 -04:00
|
|
|
insnContext = IC_VEX_L_OPSIZE;
|
2018-07-28 06:51:19 -04:00
|
|
|
else if (OpPrefix == X86Local::PD && (VEX_WPrefix == X86Local::VEX_W1 ||
|
|
|
|
|
VEX_WPrefix == X86Local::VEX_W1X))
|
2011-05-02 15:34:44 -04:00
|
|
|
insnContext = IC_VEX_W_OPSIZE;
|
2014-11-24 04:08:18 -05:00
|
|
|
else if (OpPrefix == X86Local::PD)
|
2011-05-02 15:34:44 -04:00
|
|
|
insnContext = IC_VEX_OPSIZE;
|
2014-11-24 04:08:18 -05:00
|
|
|
else if (HasVEX_LPrefix && OpPrefix == X86Local::XS)
|
2011-05-02 15:34:44 -04:00
|
|
|
insnContext = IC_VEX_L_XS;
|
2014-11-24 04:08:18 -05:00
|
|
|
else if (HasVEX_LPrefix && OpPrefix == X86Local::XD)
|
2011-05-02 15:34:44 -04:00
|
|
|
insnContext = IC_VEX_L_XD;
|
2018-07-28 06:51:19 -04:00
|
|
|
else if ((VEX_WPrefix == X86Local::VEX_W1 ||
|
|
|
|
|
VEX_WPrefix == X86Local::VEX_W1X) && OpPrefix == X86Local::XS)
|
2011-05-02 15:34:44 -04:00
|
|
|
insnContext = IC_VEX_W_XS;
|
2018-07-28 06:51:19 -04:00
|
|
|
else if ((VEX_WPrefix == X86Local::VEX_W1 ||
|
|
|
|
|
VEX_WPrefix == X86Local::VEX_W1X) && OpPrefix == X86Local::XD)
|
2011-05-02 15:34:44 -04:00
|
|
|
insnContext = IC_VEX_W_XD;
|
2018-07-28 06:51:19 -04:00
|
|
|
else if ((VEX_WPrefix == X86Local::VEX_W1 ||
|
|
|
|
|
VEX_WPrefix == X86Local::VEX_W1X) && OpPrefix == X86Local::PS)
|
2011-05-02 15:34:44 -04:00
|
|
|
insnContext = IC_VEX_W;
|
2014-11-24 04:08:18 -05:00
|
|
|
else if (HasVEX_LPrefix && OpPrefix == X86Local::PS)
|
2011-05-02 15:34:44 -04:00
|
|
|
insnContext = IC_VEX_L;
|
2014-11-24 04:08:18 -05:00
|
|
|
else if (OpPrefix == X86Local::XD)
|
2011-05-02 15:34:44 -04:00
|
|
|
insnContext = IC_VEX_XD;
|
2014-11-24 04:08:18 -05:00
|
|
|
else if (OpPrefix == X86Local::XS)
|
2011-05-02 15:34:44 -04:00
|
|
|
insnContext = IC_VEX_XS;
|
2014-11-24 04:08:18 -05:00
|
|
|
else if (OpPrefix == X86Local::PS)
|
2011-05-02 15:34:44 -04:00
|
|
|
insnContext = IC_VEX;
|
2014-11-24 04:08:18 -05:00
|
|
|
else {
|
|
|
|
|
errs() << "Instruction does not use a prefix: " << Name << "\n";
|
|
|
|
|
llvm_unreachable("Invalid prefix");
|
|
|
|
|
}
|
2015-01-18 11:17:27 -05:00
|
|
|
} else if (Is64Bit || HasREX_WPrefix || AdSize == X86Local::AdSize64) {
|
2014-11-24 04:08:18 -05:00
|
|
|
if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
|
2010-01-01 05:31:22 -05:00
|
|
|
insnContext = IC_64BIT_REXW_OPSIZE;
|
2015-01-18 11:17:27 -05:00
|
|
|
else if (HasREX_WPrefix && AdSize == X86Local::AdSize32)
|
|
|
|
|
insnContext = IC_64BIT_REXW_ADSIZE;
|
2014-11-24 04:08:18 -05:00
|
|
|
else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
|
2011-10-20 17:10:27 -04:00
|
|
|
insnContext = IC_64BIT_XD_OPSIZE;
|
2014-11-24 04:08:18 -05:00
|
|
|
else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
|
2011-10-20 17:10:27 -04:00
|
|
|
insnContext = IC_64BIT_XS_OPSIZE;
|
2018-07-28 06:51:19 -04:00
|
|
|
else if (AdSize == X86Local::AdSize32 && OpPrefix == X86Local::PD)
|
|
|
|
|
insnContext = IC_64BIT_OPSIZE_ADSIZE;
|
2015-01-18 11:17:27 -05:00
|
|
|
else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32)
|
|
|
|
|
insnContext = IC_64BIT_OPSIZE_ADSIZE;
|
2014-11-24 04:08:18 -05:00
|
|
|
else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
|
2010-01-01 05:31:22 -05:00
|
|
|
insnContext = IC_64BIT_OPSIZE;
|
2015-01-18 11:17:27 -05:00
|
|
|
else if (AdSize == X86Local::AdSize32)
|
2012-04-14 09:54:10 -04:00
|
|
|
insnContext = IC_64BIT_ADSIZE;
|
2014-11-24 04:08:18 -05:00
|
|
|
else if (HasREX_WPrefix && OpPrefix == X86Local::XS)
|
2012-04-14 09:54:10 -04:00
|
|
|
insnContext = IC_64BIT_REXW_XS;
|
2014-11-24 04:08:18 -05:00
|
|
|
else if (HasREX_WPrefix && OpPrefix == X86Local::XD)
|
2010-01-01 05:31:22 -05:00
|
|
|
insnContext = IC_64BIT_REXW_XD;
|
2014-11-24 04:08:18 -05:00
|
|
|
else if (OpPrefix == X86Local::XD)
|
2010-01-01 05:31:22 -05:00
|
|
|
insnContext = IC_64BIT_XD;
|
2014-11-24 04:08:18 -05:00
|
|
|
else if (OpPrefix == X86Local::XS)
|
2010-01-01 05:31:22 -05:00
|
|
|
insnContext = IC_64BIT_XS;
|
|
|
|
|
else if (HasREX_WPrefix)
|
|
|
|
|
insnContext = IC_64BIT_REXW;
|
|
|
|
|
else
|
|
|
|
|
insnContext = IC_64BIT;
|
|
|
|
|
} else {
|
2014-11-24 04:08:18 -05:00
|
|
|
if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
|
2011-10-20 17:10:27 -04:00
|
|
|
insnContext = IC_XD_OPSIZE;
|
2014-11-24 04:08:18 -05:00
|
|
|
else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
|
2011-10-20 17:10:27 -04:00
|
|
|
insnContext = IC_XS_OPSIZE;
|
2018-07-28 06:51:19 -04:00
|
|
|
else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XD)
|
|
|
|
|
insnContext = IC_XD_ADSIZE;
|
|
|
|
|
else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XS)
|
|
|
|
|
insnContext = IC_XS_ADSIZE;
|
|
|
|
|
else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::PD)
|
|
|
|
|
insnContext = IC_OPSIZE_ADSIZE;
|
2015-01-18 11:17:27 -05:00
|
|
|
else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16)
|
|
|
|
|
insnContext = IC_OPSIZE_ADSIZE;
|
2014-11-24 04:08:18 -05:00
|
|
|
else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
|
2010-01-01 05:31:22 -05:00
|
|
|
insnContext = IC_OPSIZE;
|
2015-01-18 11:17:27 -05:00
|
|
|
else if (AdSize == X86Local::AdSize16)
|
2012-04-14 09:54:10 -04:00
|
|
|
insnContext = IC_ADSIZE;
|
2014-11-24 04:08:18 -05:00
|
|
|
else if (OpPrefix == X86Local::XD)
|
2010-01-01 05:31:22 -05:00
|
|
|
insnContext = IC_XD;
|
2014-11-24 04:08:18 -05:00
|
|
|
else if (OpPrefix == X86Local::XS)
|
2010-01-01 05:31:22 -05:00
|
|
|
insnContext = IC_XS;
|
|
|
|
|
else
|
|
|
|
|
insnContext = IC;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return insnContext;
|
|
|
|
|
}
|
2012-08-15 15:34:23 -04:00
|
|
|
|
2014-11-24 04:08:18 -05:00
|
|
|
void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) {
|
|
|
|
|
// The scaling factor for AVX512 compressed displacement encoding is an
|
|
|
|
|
// instruction attribute. Adjust the ModRM encoding type to include the
|
|
|
|
|
// scale for compressed displacement.
|
2017-04-16 12:01:22 -04:00
|
|
|
if ((encoding != ENCODING_RM && encoding != ENCODING_VSIB) ||CD8_Scale == 0)
|
2014-11-24 04:08:18 -05:00
|
|
|
return;
|
|
|
|
|
encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale));
|
2017-04-16 12:01:22 -04:00
|
|
|
assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) ||
|
|
|
|
|
(encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) &&
|
|
|
|
|
"Invalid CDisp scaling");
|
2011-05-02 15:34:44 -04:00
|
|
|
}
|
|
|
|
|
|
2012-08-15 15:34:23 -04:00
|
|
|
void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
|
|
|
|
|
unsigned &physicalOperandIndex,
|
2016-07-23 16:41:05 -04:00
|
|
|
unsigned numPhysicalOperands,
|
2012-08-15 15:34:23 -04:00
|
|
|
const unsigned *operandMapping,
|
|
|
|
|
OperandEncoding (*encodingFromString)
|
|
|
|
|
(const std::string&,
|
2014-11-24 04:08:18 -05:00
|
|
|
uint8_t OpSize)) {
|
2010-01-01 05:31:22 -05:00
|
|
|
if (optional) {
|
|
|
|
|
if (physicalOperandIndex >= numPhysicalOperands)
|
|
|
|
|
return;
|
|
|
|
|
} else {
|
|
|
|
|
assert(physicalOperandIndex < numPhysicalOperands);
|
|
|
|
|
}
|
2012-08-15 15:34:23 -04:00
|
|
|
|
2010-01-01 05:31:22 -05:00
|
|
|
while (operandMapping[operandIndex] != operandIndex) {
|
|
|
|
|
Spec->operands[operandIndex].encoding = ENCODING_DUP;
|
|
|
|
|
Spec->operands[operandIndex].type =
|
|
|
|
|
(OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
|
|
|
|
|
++operandIndex;
|
|
|
|
|
}
|
2012-08-15 15:34:23 -04:00
|
|
|
|
2017-07-13 15:25:18 -04:00
|
|
|
StringRef typeName = (*Operands)[operandIndex].Rec->getName();
|
2011-05-02 15:34:44 -04:00
|
|
|
|
2014-11-24 04:08:18 -05:00
|
|
|
OperandEncoding encoding = encodingFromString(typeName, OpSize);
|
|
|
|
|
// Adjust the encoding type for an operand based on the instruction.
|
|
|
|
|
adjustOperandEncoding(encoding);
|
|
|
|
|
Spec->operands[operandIndex].encoding = encoding;
|
2012-08-15 15:34:23 -04:00
|
|
|
Spec->operands[operandIndex].type = typeFromString(typeName,
|
2014-11-24 04:08:18 -05:00
|
|
|
HasREX_WPrefix, OpSize);
|
2012-08-15 15:34:23 -04:00
|
|
|
|
2010-01-01 05:31:22 -05:00
|
|
|
++operandIndex;
|
|
|
|
|
++physicalOperandIndex;
|
|
|
|
|
}
|
|
|
|
|
|
2014-11-24 04:08:18 -05:00
|
|
|
void RecognizableInstr::emitInstructionSpecifier() {
|
2010-01-01 05:31:22 -05:00
|
|
|
Spec->name = Name;
|
2012-08-15 15:34:23 -04:00
|
|
|
|
2010-01-01 05:31:22 -05:00
|
|
|
Spec->insnContext = insnContext();
|
2012-08-15 15:34:23 -04:00
|
|
|
|
2011-02-20 07:57:14 -05:00
|
|
|
const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
|
2012-08-15 15:34:23 -04:00
|
|
|
|
2010-01-01 05:31:22 -05:00
|
|
|
unsigned numOperands = OperandList.size();
|
|
|
|
|
unsigned numPhysicalOperands = 0;
|
2012-08-15 15:34:23 -04:00
|
|
|
|
2010-01-01 05:31:22 -05:00
|
|
|
// operandMapping maps from operands in OperandList to their originals.
|
|
|
|
|
// If operandMapping[i] != i, then the entry is a duplicate.
|
|
|
|
|
unsigned operandMapping[X86_MAX_OPERANDS];
|
2012-04-14 09:54:10 -04:00
|
|
|
assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
|
2012-08-15 15:34:23 -04:00
|
|
|
|
|
|
|
|
for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
|
2015-05-27 14:44:32 -04:00
|
|
|
if (!OperandList[operandIndex].Constraints.empty()) {
|
2011-02-20 07:57:14 -05:00
|
|
|
const CGIOperandList::ConstraintInfo &Constraint =
|
2010-02-16 04:30:23 -05:00
|
|
|
OperandList[operandIndex].Constraints[0];
|
|
|
|
|
if (Constraint.isTied()) {
|
2012-08-15 15:34:23 -04:00
|
|
|
operandMapping[operandIndex] = operandIndex;
|
|
|
|
|
operandMapping[Constraint.getTiedOperand()] = operandIndex;
|
2010-01-01 05:31:22 -05:00
|
|
|
} else {
|
|
|
|
|
++numPhysicalOperands;
|
|
|
|
|
operandMapping[operandIndex] = operandIndex;
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
++numPhysicalOperands;
|
|
|
|
|
operandMapping[operandIndex] = operandIndex;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#define HANDLE_OPERAND(class) \
|
|
|
|
|
handleOperand(false, \
|
|
|
|
|
operandIndex, \
|
|
|
|
|
physicalOperandIndex, \
|
|
|
|
|
numPhysicalOperands, \
|
|
|
|
|
operandMapping, \
|
|
|
|
|
class##EncodingFromString);
|
2012-08-15 15:34:23 -04:00
|
|
|
|
2010-01-01 05:31:22 -05:00
|
|
|
#define HANDLE_OPTIONAL(class) \
|
|
|
|
|
handleOperand(true, \
|
|
|
|
|
operandIndex, \
|
|
|
|
|
physicalOperandIndex, \
|
|
|
|
|
numPhysicalOperands, \
|
|
|
|
|
operandMapping, \
|
|
|
|
|
class##EncodingFromString);
|
2012-08-15 15:34:23 -04:00
|
|
|
|
2010-01-01 05:31:22 -05:00
|
|
|
// operandIndex should always be < numOperands
|
2012-08-15 15:34:23 -04:00
|
|
|
unsigned operandIndex = 0;
|
2010-01-01 05:31:22 -05:00
|
|
|
// physicalOperandIndex should always be < numPhysicalOperands
|
|
|
|
|
unsigned physicalOperandIndex = 0;
|
2012-08-15 15:34:23 -04:00
|
|
|
|
2016-07-23 16:41:05 -04:00
|
|
|
#ifndef NDEBUG
|
2015-01-18 11:17:27 -05:00
|
|
|
// Given the set of prefix bits, how many additional operands does the
|
|
|
|
|
// instruction have?
|
|
|
|
|
unsigned additionalOperands = 0;
|
2017-01-02 14:17:04 -05:00
|
|
|
if (HasVEX_4V)
|
2015-01-18 11:17:27 -05:00
|
|
|
++additionalOperands;
|
|
|
|
|
if (HasEVEX_K)
|
|
|
|
|
++additionalOperands;
|
2016-07-23 16:41:05 -04:00
|
|
|
#endif
|
2015-01-18 11:17:27 -05:00
|
|
|
|
2010-01-01 05:31:22 -05:00
|
|
|
switch (Form) {
|
2014-11-24 04:08:18 -05:00
|
|
|
default: llvm_unreachable("Unhandled form");
|
|
|
|
|
case X86Local::RawFrmSrc:
|
|
|
|
|
HANDLE_OPERAND(relocation);
|
|
|
|
|
return;
|
|
|
|
|
case X86Local::RawFrmDst:
|
|
|
|
|
HANDLE_OPERAND(relocation);
|
|
|
|
|
return;
|
|
|
|
|
case X86Local::RawFrmDstSrc:
|
|
|
|
|
HANDLE_OPERAND(relocation);
|
|
|
|
|
HANDLE_OPERAND(relocation);
|
|
|
|
|
return;
|
2010-01-01 05:31:22 -05:00
|
|
|
case X86Local::RawFrm:
|
|
|
|
|
// Operand 1 (optional) is an address or immediate.
|
2016-07-23 16:41:05 -04:00
|
|
|
assert(numPhysicalOperands <= 1 &&
|
2010-01-01 05:31:22 -05:00
|
|
|
"Unexpected number of operands for RawFrm");
|
|
|
|
|
HANDLE_OPTIONAL(relocation)
|
|
|
|
|
break;
|
2014-11-24 04:08:18 -05:00
|
|
|
case X86Local::RawFrmMemOffs:
|
|
|
|
|
// Operand 1 is an address.
|
|
|
|
|
HANDLE_OPERAND(relocation);
|
|
|
|
|
break;
|
2010-01-01 05:31:22 -05:00
|
|
|
case X86Local::AddRegFrm:
|
|
|
|
|
// Operand 1 is added to the opcode.
|
|
|
|
|
// Operand 2 (optional) is an address.
|
|
|
|
|
assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
|
|
|
|
|
"Unexpected number of operands for AddRegFrm");
|
|
|
|
|
HANDLE_OPERAND(opcodeModifier)
|
|
|
|
|
HANDLE_OPTIONAL(relocation)
|
|
|
|
|
break;
|
|
|
|
|
case X86Local::MRMDestReg:
|
|
|
|
|
// Operand 1 is a register operand in the R/M field.
|
2015-01-18 11:17:27 -05:00
|
|
|
// - In AVX512 there may be a mask operand here -
|
2010-01-01 05:31:22 -05:00
|
|
|
// Operand 2 is a register operand in the Reg/Opcode field.
|
2011-10-20 17:10:27 -04:00
|
|
|
// - In AVX, there is a register operand in the VEX.vvvv field here -
|
2010-01-01 05:31:22 -05:00
|
|
|
// Operand 3 (optional) is an immediate.
|
2015-01-18 11:17:27 -05:00
|
|
|
assert(numPhysicalOperands >= 2 + additionalOperands &&
|
|
|
|
|
numPhysicalOperands <= 3 + additionalOperands &&
|
|
|
|
|
"Unexpected number of operands for MRMDestRegFrm");
|
2012-08-15 15:34:23 -04:00
|
|
|
|
2010-01-01 05:31:22 -05:00
|
|
|
HANDLE_OPERAND(rmRegister)
|
2015-01-18 11:17:27 -05:00
|
|
|
if (HasEVEX_K)
|
|
|
|
|
HANDLE_OPERAND(writemaskRegister)
|
2011-10-20 17:10:27 -04:00
|
|
|
|
2014-11-24 04:08:18 -05:00
|
|
|
if (HasVEX_4V)
|
2011-10-20 17:10:27 -04:00
|
|
|
// FIXME: In AVX, the register below becomes the one encoded
|
|
|
|
|
// in ModRMVEX and the one above the one in the VEX.VVVV field
|
|
|
|
|
HANDLE_OPERAND(vvvvRegister)
|
2012-08-15 15:34:23 -04:00
|
|
|
|
2010-01-01 05:31:22 -05:00
|
|
|
HANDLE_OPERAND(roRegister)
|
|
|
|
|
HANDLE_OPTIONAL(immediate)
|
|
|
|
|
break;
|
|
|
|
|
case X86Local::MRMDestMem:
|
|
|
|
|
// Operand 1 is a memory operand (possibly SIB-extended)
|
|
|
|
|
// Operand 2 is a register operand in the Reg/Opcode field.
|
2011-10-20 17:10:27 -04:00
|
|
|
// - In AVX, there is a register operand in the VEX.vvvv field here -
|
2010-01-01 05:31:22 -05:00
|
|
|
// Operand 3 (optional) is an immediate.
|
2015-01-18 11:17:27 -05:00
|
|
|
assert(numPhysicalOperands >= 2 + additionalOperands &&
|
|
|
|
|
numPhysicalOperands <= 3 + additionalOperands &&
|
|
|
|
|
"Unexpected number of operands for MRMDestMemFrm with VEX_4V");
|
|
|
|
|
|
2010-01-01 05:31:22 -05:00
|
|
|
HANDLE_OPERAND(memory)
|
2011-10-20 17:10:27 -04:00
|
|
|
|
2013-12-21 19:04:03 -05:00
|
|
|
if (HasEVEX_K)
|
|
|
|
|
HANDLE_OPERAND(writemaskRegister)
|
|
|
|
|
|
2014-11-24 04:08:18 -05:00
|
|
|
if (HasVEX_4V)
|
2011-10-20 17:10:27 -04:00
|
|
|
// FIXME: In AVX, the register below becomes the one encoded
|
|
|
|
|
// in ModRMVEX and the one above the one in the VEX.VVVV field
|
|
|
|
|
HANDLE_OPERAND(vvvvRegister)
|
2012-08-15 15:34:23 -04:00
|
|
|
|
2010-01-01 05:31:22 -05:00
|
|
|
HANDLE_OPERAND(roRegister)
|
|
|
|
|
HANDLE_OPTIONAL(immediate)
|
|
|
|
|
break;
|
|
|
|
|
case X86Local::MRMSrcReg:
|
|
|
|
|
// Operand 1 is a register operand in the Reg/Opcode field.
|
|
|
|
|
// Operand 2 is a register operand in the R/M field.
|
2011-05-02 15:34:44 -04:00
|
|
|
// - In AVX, there is a register operand in the VEX.vvvv field here -
|
2010-01-01 05:31:22 -05:00
|
|
|
// Operand 3 (optional) is an immediate.
|
2012-08-15 15:34:23 -04:00
|
|
|
// Operand 4 (optional) is an immediate.
|
2010-07-13 13:19:57 -04:00
|
|
|
|
2015-01-18 11:17:27 -05:00
|
|
|
assert(numPhysicalOperands >= 2 + additionalOperands &&
|
|
|
|
|
numPhysicalOperands <= 4 + additionalOperands &&
|
|
|
|
|
"Unexpected number of operands for MRMSrcRegFrm");
|
2012-08-15 15:34:23 -04:00
|
|
|
|
2011-05-02 15:34:44 -04:00
|
|
|
HANDLE_OPERAND(roRegister)
|
2012-04-14 09:54:10 -04:00
|
|
|
|
2013-12-21 19:04:03 -05:00
|
|
|
if (HasEVEX_K)
|
|
|
|
|
HANDLE_OPERAND(writemaskRegister)
|
|
|
|
|
|
2014-11-24 04:08:18 -05:00
|
|
|
if (HasVEX_4V)
|
2010-07-13 13:19:57 -04:00
|
|
|
// FIXME: In AVX, the register below becomes the one encoded
|
|
|
|
|
// in ModRMVEX and the one above the one in the VEX.VVVV field
|
2011-05-02 15:34:44 -04:00
|
|
|
HANDLE_OPERAND(vvvvRegister)
|
2012-04-14 09:54:10 -04:00
|
|
|
|
2011-05-02 15:34:44 -04:00
|
|
|
HANDLE_OPERAND(rmRegister)
|
2017-01-02 14:17:04 -05:00
|
|
|
HANDLE_OPTIONAL(immediate)
|
2012-04-14 09:54:10 -04:00
|
|
|
HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
|
2010-01-01 05:31:22 -05:00
|
|
|
break;
|
2017-01-02 14:17:04 -05:00
|
|
|
case X86Local::MRMSrcReg4VOp3:
|
|
|
|
|
assert(numPhysicalOperands == 3 &&
|
2017-05-02 14:30:13 -04:00
|
|
|
"Unexpected number of operands for MRMSrcReg4VOp3Frm");
|
2017-01-02 14:17:04 -05:00
|
|
|
HANDLE_OPERAND(roRegister)
|
|
|
|
|
HANDLE_OPERAND(rmRegister)
|
|
|
|
|
HANDLE_OPERAND(vvvvRegister)
|
|
|
|
|
break;
|
|
|
|
|
case X86Local::MRMSrcRegOp4:
|
|
|
|
|
assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 &&
|
|
|
|
|
"Unexpected number of operands for MRMSrcRegOp4Frm");
|
|
|
|
|
HANDLE_OPERAND(roRegister)
|
|
|
|
|
HANDLE_OPERAND(vvvvRegister)
|
|
|
|
|
HANDLE_OPERAND(immediate) // Register in imm[7:4]
|
|
|
|
|
HANDLE_OPERAND(rmRegister)
|
|
|
|
|
HANDLE_OPTIONAL(immediate)
|
|
|
|
|
break;
|
2010-01-01 05:31:22 -05:00
|
|
|
case X86Local::MRMSrcMem:
|
|
|
|
|
// Operand 1 is a register operand in the Reg/Opcode field.
|
|
|
|
|
// Operand 2 is a memory operand (possibly SIB-extended)
|
2011-05-02 15:34:44 -04:00
|
|
|
// - In AVX, there is a register operand in the VEX.vvvv field here -
|
2010-01-01 05:31:22 -05:00
|
|
|
// Operand 3 (optional) is an immediate.
|
2012-04-14 09:54:10 -04:00
|
|
|
|
2015-01-18 11:17:27 -05:00
|
|
|
assert(numPhysicalOperands >= 2 + additionalOperands &&
|
|
|
|
|
numPhysicalOperands <= 4 + additionalOperands &&
|
|
|
|
|
"Unexpected number of operands for MRMSrcMemFrm");
|
2012-08-15 15:34:23 -04:00
|
|
|
|
2010-01-01 05:31:22 -05:00
|
|
|
HANDLE_OPERAND(roRegister)
|
2010-07-13 13:19:57 -04:00
|
|
|
|
2013-12-21 19:04:03 -05:00
|
|
|
if (HasEVEX_K)
|
|
|
|
|
HANDLE_OPERAND(writemaskRegister)
|
|
|
|
|
|
2014-11-24 04:08:18 -05:00
|
|
|
if (HasVEX_4V)
|
2010-07-13 13:19:57 -04:00
|
|
|
// FIXME: In AVX, the register below becomes the one encoded
|
|
|
|
|
// in ModRMVEX and the one above the one in the VEX.VVVV field
|
2011-05-02 15:34:44 -04:00
|
|
|
HANDLE_OPERAND(vvvvRegister)
|
2010-07-13 13:19:57 -04:00
|
|
|
|
2010-01-01 05:31:22 -05:00
|
|
|
HANDLE_OPERAND(memory)
|
2017-01-02 14:17:04 -05:00
|
|
|
HANDLE_OPTIONAL(immediate)
|
2012-04-14 09:54:10 -04:00
|
|
|
HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
|
2010-01-01 05:31:22 -05:00
|
|
|
break;
|
2017-01-02 14:17:04 -05:00
|
|
|
case X86Local::MRMSrcMem4VOp3:
|
|
|
|
|
assert(numPhysicalOperands == 3 &&
|
2017-05-02 14:30:13 -04:00
|
|
|
"Unexpected number of operands for MRMSrcMem4VOp3Frm");
|
2017-01-02 14:17:04 -05:00
|
|
|
HANDLE_OPERAND(roRegister)
|
|
|
|
|
HANDLE_OPERAND(memory)
|
|
|
|
|
HANDLE_OPERAND(vvvvRegister)
|
|
|
|
|
break;
|
|
|
|
|
case X86Local::MRMSrcMemOp4:
|
|
|
|
|
assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 &&
|
|
|
|
|
"Unexpected number of operands for MRMSrcMemOp4Frm");
|
|
|
|
|
HANDLE_OPERAND(roRegister)
|
|
|
|
|
HANDLE_OPERAND(vvvvRegister)
|
|
|
|
|
HANDLE_OPERAND(immediate) // Register in imm[7:4]
|
|
|
|
|
HANDLE_OPERAND(memory)
|
|
|
|
|
HANDLE_OPTIONAL(immediate)
|
|
|
|
|
break;
|
2014-11-24 04:08:18 -05:00
|
|
|
case X86Local::MRMXr:
|
2010-01-01 05:31:22 -05:00
|
|
|
case X86Local::MRM0r:
|
|
|
|
|
case X86Local::MRM1r:
|
|
|
|
|
case X86Local::MRM2r:
|
|
|
|
|
case X86Local::MRM3r:
|
|
|
|
|
case X86Local::MRM4r:
|
|
|
|
|
case X86Local::MRM5r:
|
|
|
|
|
case X86Local::MRM6r:
|
|
|
|
|
case X86Local::MRM7r:
|
2015-01-18 11:17:27 -05:00
|
|
|
// Operand 1 is a register operand in the R/M field.
|
|
|
|
|
// Operand 2 (optional) is an immediate or relocation.
|
|
|
|
|
// Operand 3 (optional) is an immediate.
|
|
|
|
|
assert(numPhysicalOperands >= 0 + additionalOperands &&
|
|
|
|
|
numPhysicalOperands <= 3 + additionalOperands &&
|
|
|
|
|
"Unexpected number of operands for MRMnr");
|
|
|
|
|
|
2014-11-24 04:08:18 -05:00
|
|
|
if (HasVEX_4V)
|
2012-04-14 09:54:10 -04:00
|
|
|
HANDLE_OPERAND(vvvvRegister)
|
2013-12-21 19:04:03 -05:00
|
|
|
|
|
|
|
|
if (HasEVEX_K)
|
|
|
|
|
HANDLE_OPERAND(writemaskRegister)
|
2010-01-01 05:31:22 -05:00
|
|
|
HANDLE_OPTIONAL(rmRegister)
|
|
|
|
|
HANDLE_OPTIONAL(relocation)
|
2012-08-15 15:34:23 -04:00
|
|
|
HANDLE_OPTIONAL(immediate)
|
2010-01-01 05:31:22 -05:00
|
|
|
break;
|
2014-11-24 04:08:18 -05:00
|
|
|
case X86Local::MRMXm:
|
2010-01-01 05:31:22 -05:00
|
|
|
case X86Local::MRM0m:
|
|
|
|
|
case X86Local::MRM1m:
|
|
|
|
|
case X86Local::MRM2m:
|
|
|
|
|
case X86Local::MRM3m:
|
|
|
|
|
case X86Local::MRM4m:
|
|
|
|
|
case X86Local::MRM5m:
|
|
|
|
|
case X86Local::MRM6m:
|
|
|
|
|
case X86Local::MRM7m:
|
2015-01-18 11:17:27 -05:00
|
|
|
// Operand 1 is a memory operand (possibly SIB-extended)
|
|
|
|
|
// Operand 2 (optional) is an immediate or relocation.
|
|
|
|
|
assert(numPhysicalOperands >= 1 + additionalOperands &&
|
|
|
|
|
numPhysicalOperands <= 2 + additionalOperands &&
|
|
|
|
|
"Unexpected number of operands for MRMnm");
|
|
|
|
|
|
2014-11-24 04:08:18 -05:00
|
|
|
if (HasVEX_4V)
|
2012-04-14 09:54:10 -04:00
|
|
|
HANDLE_OPERAND(vvvvRegister)
|
2013-12-21 19:04:03 -05:00
|
|
|
if (HasEVEX_K)
|
|
|
|
|
HANDLE_OPERAND(writemaskRegister)
|
2010-01-01 05:31:22 -05:00
|
|
|
HANDLE_OPERAND(memory)
|
|
|
|
|
HANDLE_OPTIONAL(relocation)
|
|
|
|
|
break;
|
2011-02-20 07:57:14 -05:00
|
|
|
case X86Local::RawFrmImm8:
|
|
|
|
|
// operand 1 is a 16-bit immediate
|
|
|
|
|
// operand 2 is an 8-bit immediate
|
|
|
|
|
assert(numPhysicalOperands == 2 &&
|
|
|
|
|
"Unexpected number of operands for X86Local::RawFrmImm8");
|
|
|
|
|
HANDLE_OPERAND(immediate)
|
|
|
|
|
HANDLE_OPERAND(immediate)
|
|
|
|
|
break;
|
|
|
|
|
case X86Local::RawFrmImm16:
|
|
|
|
|
// operand 1 is a 16-bit immediate
|
|
|
|
|
// operand 2 is a 16-bit immediate
|
|
|
|
|
HANDLE_OPERAND(immediate)
|
|
|
|
|
HANDLE_OPERAND(immediate)
|
|
|
|
|
break;
|
2018-07-28 06:51:19 -04:00
|
|
|
#define MAP(from, to) case X86Local::MRM_##from:
|
|
|
|
|
X86_INSTR_MRM_MAPPING
|
|
|
|
|
#undef MAP
|
|
|
|
|
HANDLE_OPTIONAL(relocation)
|
2010-01-01 05:31:22 -05:00
|
|
|
break;
|
|
|
|
|
}
|
2012-08-15 15:34:23 -04:00
|
|
|
|
2018-07-28 06:51:19 -04:00
|
|
|
#undef HANDLE_OPERAND
|
|
|
|
|
#undef HANDLE_OPTIONAL
|
2010-01-01 05:31:22 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
|
|
|
|
|
// Special cases where the LLVM tables are not complete
|
|
|
|
|
|
2010-02-16 04:30:23 -05:00
|
|
|
#define MAP(from, to) \
|
2015-05-27 14:44:32 -04:00
|
|
|
case X86Local::MRM_##from:
|
2010-01-01 05:31:22 -05:00
|
|
|
|
2017-12-18 15:10:56 -05:00
|
|
|
llvm::Optional<OpcodeType> opcodeType;
|
2014-11-24 04:08:18 -05:00
|
|
|
switch (OpMap) {
|
|
|
|
|
default: llvm_unreachable("Invalid map!");
|
2018-07-28 06:51:19 -04:00
|
|
|
case X86Local::OB: opcodeType = ONEBYTE; break;
|
|
|
|
|
case X86Local::TB: opcodeType = TWOBYTE; break;
|
|
|
|
|
case X86Local::T8: opcodeType = THREEBYTE_38; break;
|
|
|
|
|
case X86Local::TA: opcodeType = THREEBYTE_3A; break;
|
|
|
|
|
case X86Local::XOP8: opcodeType = XOP8_MAP; break;
|
|
|
|
|
case X86Local::XOP9: opcodeType = XOP9_MAP; break;
|
|
|
|
|
case X86Local::XOPA: opcodeType = XOPA_MAP; break;
|
|
|
|
|
case X86Local::ThreeDNow: opcodeType = THREEDNOW_MAP; break;
|
|
|
|
|
}
|
2014-11-24 04:08:18 -05:00
|
|
|
|
2018-07-28 06:51:19 -04:00
|
|
|
std::unique_ptr<ModRMFilter> filter;
|
|
|
|
|
switch (Form) {
|
|
|
|
|
default: llvm_unreachable("Invalid form!");
|
|
|
|
|
case X86Local::Pseudo: llvm_unreachable("Pseudo should not be emitted!");
|
|
|
|
|
case X86Local::RawFrm:
|
|
|
|
|
case X86Local::AddRegFrm:
|
|
|
|
|
case X86Local::RawFrmMemOffs:
|
|
|
|
|
case X86Local::RawFrmSrc:
|
|
|
|
|
case X86Local::RawFrmDst:
|
|
|
|
|
case X86Local::RawFrmDstSrc:
|
|
|
|
|
case X86Local::RawFrmImm8:
|
|
|
|
|
case X86Local::RawFrmImm16:
|
|
|
|
|
filter = llvm::make_unique<DumbFilter>();
|
2014-11-24 04:08:18 -05:00
|
|
|
break;
|
2018-07-28 06:51:19 -04:00
|
|
|
case X86Local::MRMDestReg:
|
|
|
|
|
case X86Local::MRMSrcReg:
|
|
|
|
|
case X86Local::MRMSrcReg4VOp3:
|
|
|
|
|
case X86Local::MRMSrcRegOp4:
|
|
|
|
|
case X86Local::MRMXr:
|
|
|
|
|
filter = llvm::make_unique<ModFilter>(true);
|
|
|
|
|
break;
|
|
|
|
|
case X86Local::MRMDestMem:
|
|
|
|
|
case X86Local::MRMSrcMem:
|
|
|
|
|
case X86Local::MRMSrcMem4VOp3:
|
|
|
|
|
case X86Local::MRMSrcMemOp4:
|
|
|
|
|
case X86Local::MRMXm:
|
|
|
|
|
filter = llvm::make_unique<ModFilter>(false);
|
|
|
|
|
break;
|
|
|
|
|
case X86Local::MRM0r: case X86Local::MRM1r:
|
|
|
|
|
case X86Local::MRM2r: case X86Local::MRM3r:
|
|
|
|
|
case X86Local::MRM4r: case X86Local::MRM5r:
|
|
|
|
|
case X86Local::MRM6r: case X86Local::MRM7r:
|
|
|
|
|
filter = llvm::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r);
|
|
|
|
|
break;
|
|
|
|
|
case X86Local::MRM0m: case X86Local::MRM1m:
|
|
|
|
|
case X86Local::MRM2m: case X86Local::MRM3m:
|
|
|
|
|
case X86Local::MRM4m: case X86Local::MRM5m:
|
|
|
|
|
case X86Local::MRM6m: case X86Local::MRM7m:
|
|
|
|
|
filter = llvm::make_unique<ExtendedFilter>(false, Form - X86Local::MRM0m);
|
|
|
|
|
break;
|
|
|
|
|
X86_INSTR_MRM_MAPPING
|
|
|
|
|
filter = llvm::make_unique<ExactFilter>(0xC0 + Form - X86Local::MRM_C0);
|
|
|
|
|
break;
|
|
|
|
|
} // switch (Form)
|
|
|
|
|
|
|
|
|
|
uint8_t opcodeToSet = Opcode;
|
2010-01-01 05:31:22 -05:00
|
|
|
|
2015-01-18 11:17:27 -05:00
|
|
|
unsigned AddressSize = 0;
|
|
|
|
|
switch (AdSize) {
|
|
|
|
|
case X86Local::AdSize16: AddressSize = 16; break;
|
|
|
|
|
case X86Local::AdSize32: AddressSize = 32; break;
|
|
|
|
|
case X86Local::AdSize64: AddressSize = 64; break;
|
|
|
|
|
}
|
|
|
|
|
|
2017-12-18 15:10:56 -05:00
|
|
|
assert(opcodeType && "Opcode type not set");
|
2010-01-01 05:31:22 -05:00
|
|
|
assert(filter && "Filter not set");
|
|
|
|
|
|
|
|
|
|
if (Form == X86Local::AddRegFrm) {
|
2014-11-24 04:08:18 -05:00
|
|
|
assert(((opcodeToSet & 7) == 0) &&
|
|
|
|
|
"ADDREG_FRM opcode not aligned");
|
|
|
|
|
|
|
|
|
|
uint8_t currentOpcode;
|
|
|
|
|
|
|
|
|
|
for (currentOpcode = opcodeToSet;
|
|
|
|
|
currentOpcode < opcodeToSet + 8;
|
|
|
|
|
++currentOpcode)
|
2017-12-18 15:10:56 -05:00
|
|
|
tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter,
|
|
|
|
|
UID, Is32Bit, OpPrefix == 0,
|
|
|
|
|
IgnoresVEX_L || EncodeRC,
|
|
|
|
|
VEX_WPrefix == X86Local::VEX_WIG, AddressSize);
|
2010-01-01 05:31:22 -05:00
|
|
|
} else {
|
2017-12-18 15:10:56 -05:00
|
|
|
tables.setTableFields(*opcodeType, insnContext(), opcodeToSet, *filter, UID,
|
|
|
|
|
Is32Bit, OpPrefix == 0, IgnoresVEX_L || EncodeRC,
|
|
|
|
|
VEX_WPrefix == X86Local::VEX_WIG, AddressSize);
|
2010-01-01 05:31:22 -05:00
|
|
|
}
|
2012-08-15 15:34:23 -04:00
|
|
|
|
2010-02-16 04:30:23 -05:00
|
|
|
#undef MAP
|
2010-01-01 05:31:22 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#define TYPE(str, type) if (s == str) return type;
|
|
|
|
|
OperandType RecognizableInstr::typeFromString(const std::string &s,
|
|
|
|
|
bool hasREX_WPrefix,
|
2014-11-24 04:08:18 -05:00
|
|
|
uint8_t OpSize) {
|
2010-01-01 05:31:22 -05:00
|
|
|
if(hasREX_WPrefix) {
|
|
|
|
|
// For instructions with a REX_W prefix, a declared 32-bit register encoding
|
|
|
|
|
// is special.
|
|
|
|
|
TYPE("GR32", TYPE_R32)
|
|
|
|
|
}
|
2014-11-24 04:08:18 -05:00
|
|
|
if(OpSize == X86Local::OpSize16) {
|
|
|
|
|
// For OpSize16 instructions, a declared 16-bit register or
|
|
|
|
|
// immediate encoding is special.
|
|
|
|
|
TYPE("GR16", TYPE_Rv)
|
|
|
|
|
} else if(OpSize == X86Local::OpSize32) {
|
|
|
|
|
// For OpSize32 instructions, a declared 32-bit register or
|
2010-01-01 05:31:22 -05:00
|
|
|
// immediate encoding is special.
|
2014-11-24 04:08:18 -05:00
|
|
|
TYPE("GR32", TYPE_Rv)
|
2010-01-01 05:31:22 -05:00
|
|
|
}
|
2017-04-16 12:01:22 -04:00
|
|
|
TYPE("i16mem", TYPE_M)
|
|
|
|
|
TYPE("i16imm", TYPE_IMM)
|
|
|
|
|
TYPE("i16i8imm", TYPE_IMM)
|
2014-11-24 04:08:18 -05:00
|
|
|
TYPE("GR16", TYPE_R16)
|
2017-04-16 12:01:22 -04:00
|
|
|
TYPE("i32mem", TYPE_M)
|
|
|
|
|
TYPE("i32imm", TYPE_IMM)
|
|
|
|
|
TYPE("i32i8imm", TYPE_IMM)
|
2014-11-24 04:08:18 -05:00
|
|
|
TYPE("GR32", TYPE_R32)
|
2013-12-21 19:04:03 -05:00
|
|
|
TYPE("GR32orGR64", TYPE_R32)
|
2017-04-16 12:01:22 -04:00
|
|
|
TYPE("i64mem", TYPE_M)
|
|
|
|
|
TYPE("i64i32imm", TYPE_IMM)
|
|
|
|
|
TYPE("i64i8imm", TYPE_IMM)
|
2010-01-01 05:31:22 -05:00
|
|
|
TYPE("GR64", TYPE_R64)
|
2017-04-16 12:01:22 -04:00
|
|
|
TYPE("i8mem", TYPE_M)
|
|
|
|
|
TYPE("i8imm", TYPE_IMM)
|
2015-05-27 14:44:32 -04:00
|
|
|
TYPE("u8imm", TYPE_UIMM8)
|
|
|
|
|
TYPE("i32u8imm", TYPE_UIMM8)
|
2010-01-01 05:31:22 -05:00
|
|
|
TYPE("GR8", TYPE_R8)
|
2017-04-16 12:01:22 -04:00
|
|
|
TYPE("VR128", TYPE_XMM)
|
|
|
|
|
TYPE("VR128X", TYPE_XMM)
|
|
|
|
|
TYPE("f128mem", TYPE_M)
|
|
|
|
|
TYPE("f256mem", TYPE_M)
|
|
|
|
|
TYPE("f512mem", TYPE_M)
|
|
|
|
|
TYPE("FR128", TYPE_XMM)
|
|
|
|
|
TYPE("FR64", TYPE_XMM)
|
|
|
|
|
TYPE("FR64X", TYPE_XMM)
|
|
|
|
|
TYPE("f64mem", TYPE_M)
|
|
|
|
|
TYPE("sdmem", TYPE_M)
|
|
|
|
|
TYPE("FR32", TYPE_XMM)
|
|
|
|
|
TYPE("FR32X", TYPE_XMM)
|
|
|
|
|
TYPE("f32mem", TYPE_M)
|
|
|
|
|
TYPE("ssmem", TYPE_M)
|
2010-01-01 05:31:22 -05:00
|
|
|
TYPE("RST", TYPE_ST)
|
Pull in r352607 from upstream llvm trunk (by Craig Topper):
[X86] Add FPSW as a Def on some FP instructions that were missing it.
Pull in r352608 from upstream llvm trunk (by Craig Topper):
[X86] Remove a couple places where we unnecessarily pass 0 to the
EmitPriority of some FP instruction aliases. NFC
As far as I can tell we already won't emit these aliases due to an
operand count check in the tablegen code. Removing these because I
couldn't make sense of the inconsistency between fadd and fmul from
reading the code.
I checked the AsmMatcher and AsmWriter files before and after this
change and there were no differences.
Pull in r353015 from upstream llvm trunk (by Craig Topper):
[X86] Print %st(0) as %st when its implicit to the instruction.
Continue printing it as %st(0) when its encoded in the instruction.
This is a step back from the change I made in r352985. This appears
to be more consistent with gcc and objdump behavior.
Pull in r353061 from upstream llvm trunk (by Craig Topper):
[X86] Print all register forms of x87 fadd/fsub/fdiv/fmul as having
two arguments where on is %st.
All of these instructions consume one encoded register and the other
register is %st. They either write the result to %st or the encoded
register. Previously we printed both arguments when the encoded
register was written. And we printed one argument when the result was
written to %st. For the stack popping forms the encoded register is
always the destination and we didn't print both operands. This was
inconsistent with gcc and objdump and just makes the output assembly
code harder to read.
This patch changes things to always print both operands making us
consistent with gcc and objdump. The parser should still be able to
handle the single register forms just as it did before. This also
matches the GNU assembler behavior.
Pull in r353141 from upstream llvm trunk (by Craig Topper):
[X86] Connect the default fpsr and dirflag clobbers in inline
assembly to the registers we have defined for them.
Summary:
We don't currently map these constraints to physical register numbers
so they don't make it to the MachineIR representation of inline
assembly.
This could have problems for proper dependency tracking in the
machine schedulers though I don't have a test case that shows that.
Reviewers: rnk
Reviewed By: rnk
Subscribers: eraman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D57641
Pull in r353489 from upstream llvm trunk (by Craig Topper):
[X86] Add FPCW as a register and start using it as an implicit use on
floating point instructions.
Summary:
FPCW contains the rounding mode control which we manipulate to
implement fp to integer conversion by changing the roudning mode,
storing the value to the stack, and then changing the rounding mode
back. Because we didn't model FPCW and its dependency chain, other
instructions could be scheduled into the middle of the sequence.
This patch introduces the register and adds it as an implciit def of
FLDCW and implicit use of the FP binary arithmetic instructions and
store instructions. There are more instructions that need to be
updated, but this is a good start. I believe this fixes at least the
reduced test case from PR40529.
Reviewers: RKSimon, spatel, rnk, efriedma, andrew.w.kaylor
Subscribers: dim, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D57735
These should fix a problem in clang 7.0 where it would sometimes emit
long double floating point instructions in a slightly wrong order,
leading to failures in our libm tests. In particular, the cbrt_test
test case 'cbrtl_powl' and the trig_test test case 'reduction'.
Reported by: lwhsu
PR: 234040
Upstream PR: https://bugs.llvm.org/show_bug.cgi?id=40206
2019-02-10 07:45:33 -05:00
|
|
|
TYPE("RSTi", TYPE_ST)
|
2017-04-16 12:01:22 -04:00
|
|
|
TYPE("i128mem", TYPE_M)
|
|
|
|
|
TYPE("i256mem", TYPE_M)
|
|
|
|
|
TYPE("i512mem", TYPE_M)
|
|
|
|
|
TYPE("i64i32imm_pcrel", TYPE_REL)
|
|
|
|
|
TYPE("i16imm_pcrel", TYPE_REL)
|
|
|
|
|
TYPE("i32imm_pcrel", TYPE_REL)
|
2010-05-04 12:11:02 -04:00
|
|
|
TYPE("SSECC", TYPE_IMM3)
|
2015-05-27 14:44:32 -04:00
|
|
|
TYPE("XOPCC", TYPE_IMM3)
|
2012-04-14 09:54:10 -04:00
|
|
|
TYPE("AVXCC", TYPE_IMM5)
|
2015-05-27 14:44:32 -04:00
|
|
|
TYPE("AVX512ICC", TYPE_AVX512ICC)
|
2017-04-16 12:01:22 -04:00
|
|
|
TYPE("AVX512RC", TYPE_IMM)
|
|
|
|
|
TYPE("brtarget32", TYPE_REL)
|
|
|
|
|
TYPE("brtarget16", TYPE_REL)
|
|
|
|
|
TYPE("brtarget8", TYPE_REL)
|
|
|
|
|
TYPE("f80mem", TYPE_M)
|
|
|
|
|
TYPE("lea64_32mem", TYPE_M)
|
|
|
|
|
TYPE("lea64mem", TYPE_M)
|
2010-01-01 05:31:22 -05:00
|
|
|
TYPE("VR64", TYPE_MM64)
|
2017-04-16 12:01:22 -04:00
|
|
|
TYPE("i64imm", TYPE_IMM)
|
2015-01-18 11:17:27 -05:00
|
|
|
TYPE("anymem", TYPE_M)
|
2018-07-28 06:51:19 -04:00
|
|
|
TYPE("opaquemem", TYPE_M)
|
2010-01-01 05:31:22 -05:00
|
|
|
TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
|
|
|
|
|
TYPE("DEBUG_REG", TYPE_DEBUGREG)
|
2010-05-27 11:15:58 -04:00
|
|
|
TYPE("CONTROL_REG", TYPE_CONTROLREG)
|
2017-04-16 12:01:22 -04:00
|
|
|
TYPE("srcidx8", TYPE_SRCIDX)
|
|
|
|
|
TYPE("srcidx16", TYPE_SRCIDX)
|
|
|
|
|
TYPE("srcidx32", TYPE_SRCIDX)
|
|
|
|
|
TYPE("srcidx64", TYPE_SRCIDX)
|
|
|
|
|
TYPE("dstidx8", TYPE_DSTIDX)
|
|
|
|
|
TYPE("dstidx16", TYPE_DSTIDX)
|
|
|
|
|
TYPE("dstidx32", TYPE_DSTIDX)
|
|
|
|
|
TYPE("dstidx64", TYPE_DSTIDX)
|
|
|
|
|
TYPE("offset16_8", TYPE_MOFFS)
|
|
|
|
|
TYPE("offset16_16", TYPE_MOFFS)
|
|
|
|
|
TYPE("offset16_32", TYPE_MOFFS)
|
|
|
|
|
TYPE("offset32_8", TYPE_MOFFS)
|
|
|
|
|
TYPE("offset32_16", TYPE_MOFFS)
|
|
|
|
|
TYPE("offset32_32", TYPE_MOFFS)
|
|
|
|
|
TYPE("offset32_64", TYPE_MOFFS)
|
|
|
|
|
TYPE("offset64_8", TYPE_MOFFS)
|
|
|
|
|
TYPE("offset64_16", TYPE_MOFFS)
|
|
|
|
|
TYPE("offset64_32", TYPE_MOFFS)
|
|
|
|
|
TYPE("offset64_64", TYPE_MOFFS)
|
|
|
|
|
TYPE("VR256", TYPE_YMM)
|
|
|
|
|
TYPE("VR256X", TYPE_YMM)
|
|
|
|
|
TYPE("VR512", TYPE_ZMM)
|
|
|
|
|
TYPE("VK1", TYPE_VK)
|
|
|
|
|
TYPE("VK1WM", TYPE_VK)
|
|
|
|
|
TYPE("VK2", TYPE_VK)
|
|
|
|
|
TYPE("VK2WM", TYPE_VK)
|
|
|
|
|
TYPE("VK4", TYPE_VK)
|
|
|
|
|
TYPE("VK4WM", TYPE_VK)
|
|
|
|
|
TYPE("VK8", TYPE_VK)
|
|
|
|
|
TYPE("VK8WM", TYPE_VK)
|
|
|
|
|
TYPE("VK16", TYPE_VK)
|
|
|
|
|
TYPE("VK16WM", TYPE_VK)
|
|
|
|
|
TYPE("VK32", TYPE_VK)
|
|
|
|
|
TYPE("VK32WM", TYPE_VK)
|
|
|
|
|
TYPE("VK64", TYPE_VK)
|
|
|
|
|
TYPE("VK64WM", TYPE_VK)
|
2017-12-18 15:10:56 -05:00
|
|
|
TYPE("vx64mem", TYPE_MVSIBX)
|
|
|
|
|
TYPE("vx128mem", TYPE_MVSIBX)
|
|
|
|
|
TYPE("vx256mem", TYPE_MVSIBX)
|
|
|
|
|
TYPE("vy128mem", TYPE_MVSIBY)
|
|
|
|
|
TYPE("vy256mem", TYPE_MVSIBY)
|
|
|
|
|
TYPE("vx64xmem", TYPE_MVSIBX)
|
|
|
|
|
TYPE("vx128xmem", TYPE_MVSIBX)
|
|
|
|
|
TYPE("vx256xmem", TYPE_MVSIBX)
|
|
|
|
|
TYPE("vy128xmem", TYPE_MVSIBY)
|
|
|
|
|
TYPE("vy256xmem", TYPE_MVSIBY)
|
2018-07-28 06:51:19 -04:00
|
|
|
TYPE("vy512xmem", TYPE_MVSIBY)
|
|
|
|
|
TYPE("vz256mem", TYPE_MVSIBZ)
|
2017-12-18 15:10:56 -05:00
|
|
|
TYPE("vz512mem", TYPE_MVSIBZ)
|
2015-06-09 15:06:30 -04:00
|
|
|
TYPE("BNDR", TYPE_BNDR)
|
2010-01-01 05:31:22 -05:00
|
|
|
errs() << "Unhandled type string " << s << "\n";
|
|
|
|
|
llvm_unreachable("Unhandled type string");
|
|
|
|
|
}
|
|
|
|
|
#undef TYPE
|
|
|
|
|
|
|
|
|
|
#define ENCODING(str, encoding) if (s == str) return encoding;
|
2014-11-24 04:08:18 -05:00
|
|
|
OperandEncoding
|
|
|
|
|
RecognizableInstr::immediateEncodingFromString(const std::string &s,
|
|
|
|
|
uint8_t OpSize) {
|
|
|
|
|
if(OpSize != X86Local::OpSize16) {
|
2010-01-01 05:31:22 -05:00
|
|
|
// For instructions without an OpSize prefix, a declared 16-bit register or
|
|
|
|
|
// immediate encoding is special.
|
|
|
|
|
ENCODING("i16imm", ENCODING_IW)
|
|
|
|
|
}
|
|
|
|
|
ENCODING("i32i8imm", ENCODING_IB)
|
|
|
|
|
ENCODING("SSECC", ENCODING_IB)
|
2015-05-27 14:44:32 -04:00
|
|
|
ENCODING("XOPCC", ENCODING_IB)
|
2012-04-14 09:54:10 -04:00
|
|
|
ENCODING("AVXCC", ENCODING_IB)
|
2015-05-27 14:44:32 -04:00
|
|
|
ENCODING("AVX512ICC", ENCODING_IB)
|
2017-12-18 15:10:56 -05:00
|
|
|
ENCODING("AVX512RC", ENCODING_IRC)
|
2010-01-01 05:31:22 -05:00
|
|
|
ENCODING("i16imm", ENCODING_Iv)
|
|
|
|
|
ENCODING("i16i8imm", ENCODING_IB)
|
|
|
|
|
ENCODING("i32imm", ENCODING_Iv)
|
|
|
|
|
ENCODING("i64i32imm", ENCODING_ID)
|
|
|
|
|
ENCODING("i64i8imm", ENCODING_IB)
|
|
|
|
|
ENCODING("i8imm", ENCODING_IB)
|
2015-05-27 14:44:32 -04:00
|
|
|
ENCODING("u8imm", ENCODING_IB)
|
|
|
|
|
ENCODING("i32u8imm", ENCODING_IB)
|
2011-05-02 15:34:44 -04:00
|
|
|
// This is not a typo. Instructions like BLENDVPD put
|
|
|
|
|
// register IDs in 8-bit immediates nowadays.
|
2012-12-02 08:10:19 -05:00
|
|
|
ENCODING("FR32", ENCODING_IB)
|
|
|
|
|
ENCODING("FR64", ENCODING_IB)
|
2015-12-30 06:46:15 -05:00
|
|
|
ENCODING("FR128", ENCODING_IB)
|
2013-12-21 19:04:03 -05:00
|
|
|
ENCODING("VR128", ENCODING_IB)
|
|
|
|
|
ENCODING("VR256", ENCODING_IB)
|
|
|
|
|
ENCODING("FR32X", ENCODING_IB)
|
|
|
|
|
ENCODING("FR64X", ENCODING_IB)
|
|
|
|
|
ENCODING("VR128X", ENCODING_IB)
|
|
|
|
|
ENCODING("VR256X", ENCODING_IB)
|
|
|
|
|
ENCODING("VR512", ENCODING_IB)
|
2010-01-01 05:31:22 -05:00
|
|
|
errs() << "Unhandled immediate encoding " << s << "\n";
|
|
|
|
|
llvm_unreachable("Unhandled immediate encoding");
|
|
|
|
|
}
|
|
|
|
|
|
2014-11-24 04:08:18 -05:00
|
|
|
OperandEncoding
|
|
|
|
|
RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
|
|
|
|
|
uint8_t OpSize) {
|
|
|
|
|
ENCODING("RST", ENCODING_FP)
|
Pull in r352607 from upstream llvm trunk (by Craig Topper):
[X86] Add FPSW as a Def on some FP instructions that were missing it.
Pull in r352608 from upstream llvm trunk (by Craig Topper):
[X86] Remove a couple places where we unnecessarily pass 0 to the
EmitPriority of some FP instruction aliases. NFC
As far as I can tell we already won't emit these aliases due to an
operand count check in the tablegen code. Removing these because I
couldn't make sense of the inconsistency between fadd and fmul from
reading the code.
I checked the AsmMatcher and AsmWriter files before and after this
change and there were no differences.
Pull in r353015 from upstream llvm trunk (by Craig Topper):
[X86] Print %st(0) as %st when its implicit to the instruction.
Continue printing it as %st(0) when its encoded in the instruction.
This is a step back from the change I made in r352985. This appears
to be more consistent with gcc and objdump behavior.
Pull in r353061 from upstream llvm trunk (by Craig Topper):
[X86] Print all register forms of x87 fadd/fsub/fdiv/fmul as having
two arguments where on is %st.
All of these instructions consume one encoded register and the other
register is %st. They either write the result to %st or the encoded
register. Previously we printed both arguments when the encoded
register was written. And we printed one argument when the result was
written to %st. For the stack popping forms the encoded register is
always the destination and we didn't print both operands. This was
inconsistent with gcc and objdump and just makes the output assembly
code harder to read.
This patch changes things to always print both operands making us
consistent with gcc and objdump. The parser should still be able to
handle the single register forms just as it did before. This also
matches the GNU assembler behavior.
Pull in r353141 from upstream llvm trunk (by Craig Topper):
[X86] Connect the default fpsr and dirflag clobbers in inline
assembly to the registers we have defined for them.
Summary:
We don't currently map these constraints to physical register numbers
so they don't make it to the MachineIR representation of inline
assembly.
This could have problems for proper dependency tracking in the
machine schedulers though I don't have a test case that shows that.
Reviewers: rnk
Reviewed By: rnk
Subscribers: eraman, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D57641
Pull in r353489 from upstream llvm trunk (by Craig Topper):
[X86] Add FPCW as a register and start using it as an implicit use on
floating point instructions.
Summary:
FPCW contains the rounding mode control which we manipulate to
implement fp to integer conversion by changing the roudning mode,
storing the value to the stack, and then changing the rounding mode
back. Because we didn't model FPCW and its dependency chain, other
instructions could be scheduled into the middle of the sequence.
This patch introduces the register and adds it as an implciit def of
FLDCW and implicit use of the FP binary arithmetic instructions and
store instructions. There are more instructions that need to be
updated, but this is a good start. I believe this fixes at least the
reduced test case from PR40529.
Reviewers: RKSimon, spatel, rnk, efriedma, andrew.w.kaylor
Subscribers: dim, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D57735
These should fix a problem in clang 7.0 where it would sometimes emit
long double floating point instructions in a slightly wrong order,
leading to failures in our libm tests. In particular, the cbrt_test
test case 'cbrtl_powl' and the trig_test test case 'reduction'.
Reported by: lwhsu
PR: 234040
Upstream PR: https://bugs.llvm.org/show_bug.cgi?id=40206
2019-02-10 07:45:33 -05:00
|
|
|
ENCODING("RSTi", ENCODING_FP)
|
2010-01-01 05:31:22 -05:00
|
|
|
ENCODING("GR16", ENCODING_RM)
|
|
|
|
|
ENCODING("GR32", ENCODING_RM)
|
2013-12-21 19:04:03 -05:00
|
|
|
ENCODING("GR32orGR64", ENCODING_RM)
|
2010-01-01 05:31:22 -05:00
|
|
|
ENCODING("GR64", ENCODING_RM)
|
|
|
|
|
ENCODING("GR8", ENCODING_RM)
|
|
|
|
|
ENCODING("VR128", ENCODING_RM)
|
2013-12-21 19:04:03 -05:00
|
|
|
ENCODING("VR128X", ENCODING_RM)
|
2015-12-30 06:46:15 -05:00
|
|
|
ENCODING("FR128", ENCODING_RM)
|
2010-01-01 05:31:22 -05:00
|
|
|
ENCODING("FR64", ENCODING_RM)
|
|
|
|
|
ENCODING("FR32", ENCODING_RM)
|
2013-12-21 19:04:03 -05:00
|
|
|
ENCODING("FR64X", ENCODING_RM)
|
|
|
|
|
ENCODING("FR32X", ENCODING_RM)
|
2010-01-01 05:31:22 -05:00
|
|
|
ENCODING("VR64", ENCODING_RM)
|
2011-05-02 15:34:44 -04:00
|
|
|
ENCODING("VR256", ENCODING_RM)
|
2013-12-21 19:04:03 -05:00
|
|
|
ENCODING("VR256X", ENCODING_RM)
|
|
|
|
|
ENCODING("VR512", ENCODING_RM)
|
2014-11-24 04:08:18 -05:00
|
|
|
ENCODING("VK1", ENCODING_RM)
|
2015-05-27 14:44:32 -04:00
|
|
|
ENCODING("VK2", ENCODING_RM)
|
|
|
|
|
ENCODING("VK4", ENCODING_RM)
|
2013-12-21 19:04:03 -05:00
|
|
|
ENCODING("VK8", ENCODING_RM)
|
|
|
|
|
ENCODING("VK16", ENCODING_RM)
|
2015-01-18 11:17:27 -05:00
|
|
|
ENCODING("VK32", ENCODING_RM)
|
|
|
|
|
ENCODING("VK64", ENCODING_RM)
|
2015-06-09 15:06:30 -04:00
|
|
|
ENCODING("BNDR", ENCODING_RM)
|
2010-01-01 05:31:22 -05:00
|
|
|
errs() << "Unhandled R/M register encoding " << s << "\n";
|
|
|
|
|
llvm_unreachable("Unhandled R/M register encoding");
|
|
|
|
|
}
|
|
|
|
|
|
2014-11-24 04:08:18 -05:00
|
|
|
OperandEncoding
|
|
|
|
|
RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
|
|
|
|
|
uint8_t OpSize) {
|
2010-01-01 05:31:22 -05:00
|
|
|
ENCODING("GR16", ENCODING_REG)
|
|
|
|
|
ENCODING("GR32", ENCODING_REG)
|
2013-12-21 19:04:03 -05:00
|
|
|
ENCODING("GR32orGR64", ENCODING_REG)
|
2010-01-01 05:31:22 -05:00
|
|
|
ENCODING("GR64", ENCODING_REG)
|
|
|
|
|
ENCODING("GR8", ENCODING_REG)
|
|
|
|
|
ENCODING("VR128", ENCODING_REG)
|
2015-12-30 06:46:15 -05:00
|
|
|
ENCODING("FR128", ENCODING_REG)
|
2010-01-01 05:31:22 -05:00
|
|
|
ENCODING("FR64", ENCODING_REG)
|
|
|
|
|
ENCODING("FR32", ENCODING_REG)
|
|
|
|
|
ENCODING("VR64", ENCODING_REG)
|
|
|
|
|
ENCODING("SEGMENT_REG", ENCODING_REG)
|
|
|
|
|
ENCODING("DEBUG_REG", ENCODING_REG)
|
2010-05-27 11:15:58 -04:00
|
|
|
ENCODING("CONTROL_REG", ENCODING_REG)
|
2011-05-02 15:34:44 -04:00
|
|
|
ENCODING("VR256", ENCODING_REG)
|
2013-12-21 19:04:03 -05:00
|
|
|
ENCODING("VR256X", ENCODING_REG)
|
|
|
|
|
ENCODING("VR128X", ENCODING_REG)
|
|
|
|
|
ENCODING("FR64X", ENCODING_REG)
|
|
|
|
|
ENCODING("FR32X", ENCODING_REG)
|
|
|
|
|
ENCODING("VR512", ENCODING_REG)
|
2014-11-24 04:08:18 -05:00
|
|
|
ENCODING("VK1", ENCODING_REG)
|
2015-01-18 11:17:27 -05:00
|
|
|
ENCODING("VK2", ENCODING_REG)
|
|
|
|
|
ENCODING("VK4", ENCODING_REG)
|
2013-12-21 19:04:03 -05:00
|
|
|
ENCODING("VK8", ENCODING_REG)
|
|
|
|
|
ENCODING("VK16", ENCODING_REG)
|
2015-01-18 11:17:27 -05:00
|
|
|
ENCODING("VK32", ENCODING_REG)
|
|
|
|
|
ENCODING("VK64", ENCODING_REG)
|
2014-11-24 04:08:18 -05:00
|
|
|
ENCODING("VK1WM", ENCODING_REG)
|
2015-05-27 14:44:32 -04:00
|
|
|
ENCODING("VK2WM", ENCODING_REG)
|
|
|
|
|
ENCODING("VK4WM", ENCODING_REG)
|
2013-12-21 19:04:03 -05:00
|
|
|
ENCODING("VK8WM", ENCODING_REG)
|
|
|
|
|
ENCODING("VK16WM", ENCODING_REG)
|
2015-05-27 14:44:32 -04:00
|
|
|
ENCODING("VK32WM", ENCODING_REG)
|
|
|
|
|
ENCODING("VK64WM", ENCODING_REG)
|
2015-06-09 15:06:30 -04:00
|
|
|
ENCODING("BNDR", ENCODING_REG)
|
2010-01-01 05:31:22 -05:00
|
|
|
errs() << "Unhandled reg/opcode register encoding " << s << "\n";
|
|
|
|
|
llvm_unreachable("Unhandled reg/opcode register encoding");
|
|
|
|
|
}
|
|
|
|
|
|
2014-11-24 04:08:18 -05:00
|
|
|
OperandEncoding
|
|
|
|
|
RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
|
|
|
|
|
uint8_t OpSize) {
|
2011-10-20 17:10:27 -04:00
|
|
|
ENCODING("GR32", ENCODING_VVVV)
|
|
|
|
|
ENCODING("GR64", ENCODING_VVVV)
|
2011-05-02 15:34:44 -04:00
|
|
|
ENCODING("FR32", ENCODING_VVVV)
|
2015-12-30 06:46:15 -05:00
|
|
|
ENCODING("FR128", ENCODING_VVVV)
|
2011-05-02 15:34:44 -04:00
|
|
|
ENCODING("FR64", ENCODING_VVVV)
|
|
|
|
|
ENCODING("VR128", ENCODING_VVVV)
|
|
|
|
|
ENCODING("VR256", ENCODING_VVVV)
|
2013-12-21 19:04:03 -05:00
|
|
|
ENCODING("FR32X", ENCODING_VVVV)
|
|
|
|
|
ENCODING("FR64X", ENCODING_VVVV)
|
|
|
|
|
ENCODING("VR128X", ENCODING_VVVV)
|
|
|
|
|
ENCODING("VR256X", ENCODING_VVVV)
|
|
|
|
|
ENCODING("VR512", ENCODING_VVVV)
|
2014-11-24 04:08:18 -05:00
|
|
|
ENCODING("VK1", ENCODING_VVVV)
|
|
|
|
|
ENCODING("VK2", ENCODING_VVVV)
|
|
|
|
|
ENCODING("VK4", ENCODING_VVVV)
|
2013-12-21 19:04:03 -05:00
|
|
|
ENCODING("VK8", ENCODING_VVVV)
|
|
|
|
|
ENCODING("VK16", ENCODING_VVVV)
|
2015-01-18 11:17:27 -05:00
|
|
|
ENCODING("VK32", ENCODING_VVVV)
|
|
|
|
|
ENCODING("VK64", ENCODING_VVVV)
|
2011-05-02 15:34:44 -04:00
|
|
|
errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
|
|
|
|
|
llvm_unreachable("Unhandled VEX.vvvv register encoding");
|
|
|
|
|
}
|
|
|
|
|
|
2014-11-24 04:08:18 -05:00
|
|
|
OperandEncoding
|
|
|
|
|
RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
|
|
|
|
|
uint8_t OpSize) {
|
|
|
|
|
ENCODING("VK1WM", ENCODING_WRITEMASK)
|
|
|
|
|
ENCODING("VK2WM", ENCODING_WRITEMASK)
|
|
|
|
|
ENCODING("VK4WM", ENCODING_WRITEMASK)
|
2013-12-21 19:04:03 -05:00
|
|
|
ENCODING("VK8WM", ENCODING_WRITEMASK)
|
|
|
|
|
ENCODING("VK16WM", ENCODING_WRITEMASK)
|
2014-11-24 04:08:18 -05:00
|
|
|
ENCODING("VK32WM", ENCODING_WRITEMASK)
|
|
|
|
|
ENCODING("VK64WM", ENCODING_WRITEMASK)
|
2013-12-21 19:04:03 -05:00
|
|
|
errs() << "Unhandled mask register encoding " << s << "\n";
|
|
|
|
|
llvm_unreachable("Unhandled mask register encoding");
|
|
|
|
|
}
|
|
|
|
|
|
2014-11-24 04:08:18 -05:00
|
|
|
OperandEncoding
|
|
|
|
|
RecognizableInstr::memoryEncodingFromString(const std::string &s,
|
|
|
|
|
uint8_t OpSize) {
|
2010-01-01 05:31:22 -05:00
|
|
|
ENCODING("i16mem", ENCODING_RM)
|
|
|
|
|
ENCODING("i32mem", ENCODING_RM)
|
|
|
|
|
ENCODING("i64mem", ENCODING_RM)
|
|
|
|
|
ENCODING("i8mem", ENCODING_RM)
|
2011-02-20 07:57:14 -05:00
|
|
|
ENCODING("ssmem", ENCODING_RM)
|
|
|
|
|
ENCODING("sdmem", ENCODING_RM)
|
2010-01-01 05:31:22 -05:00
|
|
|
ENCODING("f128mem", ENCODING_RM)
|
2011-02-20 07:57:14 -05:00
|
|
|
ENCODING("f256mem", ENCODING_RM)
|
2013-12-21 19:04:03 -05:00
|
|
|
ENCODING("f512mem", ENCODING_RM)
|
2010-01-01 05:31:22 -05:00
|
|
|
ENCODING("f64mem", ENCODING_RM)
|
|
|
|
|
ENCODING("f32mem", ENCODING_RM)
|
|
|
|
|
ENCODING("i128mem", ENCODING_RM)
|
2011-05-02 15:34:44 -04:00
|
|
|
ENCODING("i256mem", ENCODING_RM)
|
2013-12-21 19:04:03 -05:00
|
|
|
ENCODING("i512mem", ENCODING_RM)
|
2010-01-01 05:31:22 -05:00
|
|
|
ENCODING("f80mem", ENCODING_RM)
|
|
|
|
|
ENCODING("lea64_32mem", ENCODING_RM)
|
|
|
|
|
ENCODING("lea64mem", ENCODING_RM)
|
2015-01-18 11:17:27 -05:00
|
|
|
ENCODING("anymem", ENCODING_RM)
|
2018-07-28 06:51:19 -04:00
|
|
|
ENCODING("opaquemem", ENCODING_RM)
|
2017-04-16 12:01:22 -04:00
|
|
|
ENCODING("vx64mem", ENCODING_VSIB)
|
|
|
|
|
ENCODING("vx128mem", ENCODING_VSIB)
|
|
|
|
|
ENCODING("vx256mem", ENCODING_VSIB)
|
|
|
|
|
ENCODING("vy128mem", ENCODING_VSIB)
|
|
|
|
|
ENCODING("vy256mem", ENCODING_VSIB)
|
|
|
|
|
ENCODING("vx64xmem", ENCODING_VSIB)
|
|
|
|
|
ENCODING("vx128xmem", ENCODING_VSIB)
|
|
|
|
|
ENCODING("vx256xmem", ENCODING_VSIB)
|
|
|
|
|
ENCODING("vy128xmem", ENCODING_VSIB)
|
|
|
|
|
ENCODING("vy256xmem", ENCODING_VSIB)
|
2018-07-28 06:51:19 -04:00
|
|
|
ENCODING("vy512xmem", ENCODING_VSIB)
|
|
|
|
|
ENCODING("vz256mem", ENCODING_VSIB)
|
2017-04-16 12:01:22 -04:00
|
|
|
ENCODING("vz512mem", ENCODING_VSIB)
|
2010-01-01 05:31:22 -05:00
|
|
|
errs() << "Unhandled memory encoding " << s << "\n";
|
|
|
|
|
llvm_unreachable("Unhandled memory encoding");
|
|
|
|
|
}
|
|
|
|
|
|
2014-11-24 04:08:18 -05:00
|
|
|
OperandEncoding
|
|
|
|
|
RecognizableInstr::relocationEncodingFromString(const std::string &s,
|
|
|
|
|
uint8_t OpSize) {
|
|
|
|
|
if(OpSize != X86Local::OpSize16) {
|
2010-01-01 05:31:22 -05:00
|
|
|
// For instructions without an OpSize prefix, a declared 16-bit register or
|
|
|
|
|
// immediate encoding is special.
|
|
|
|
|
ENCODING("i16imm", ENCODING_IW)
|
|
|
|
|
}
|
|
|
|
|
ENCODING("i16imm", ENCODING_Iv)
|
|
|
|
|
ENCODING("i16i8imm", ENCODING_IB)
|
|
|
|
|
ENCODING("i32imm", ENCODING_Iv)
|
|
|
|
|
ENCODING("i32i8imm", ENCODING_IB)
|
|
|
|
|
ENCODING("i64i32imm", ENCODING_ID)
|
|
|
|
|
ENCODING("i64i8imm", ENCODING_IB)
|
|
|
|
|
ENCODING("i8imm", ENCODING_IB)
|
2015-05-27 14:44:32 -04:00
|
|
|
ENCODING("u8imm", ENCODING_IB)
|
|
|
|
|
ENCODING("i32u8imm", ENCODING_IB)
|
2010-01-01 05:31:22 -05:00
|
|
|
ENCODING("i64i32imm_pcrel", ENCODING_ID)
|
2010-07-13 13:19:57 -04:00
|
|
|
ENCODING("i16imm_pcrel", ENCODING_IW)
|
2010-01-01 05:31:22 -05:00
|
|
|
ENCODING("i32imm_pcrel", ENCODING_ID)
|
2019-01-19 05:01:25 -05:00
|
|
|
ENCODING("brtarget32", ENCODING_ID)
|
|
|
|
|
ENCODING("brtarget16", ENCODING_IW)
|
2010-01-01 05:31:22 -05:00
|
|
|
ENCODING("brtarget8", ENCODING_IB)
|
|
|
|
|
ENCODING("i64imm", ENCODING_IO)
|
2015-01-18 11:17:27 -05:00
|
|
|
ENCODING("offset16_8", ENCODING_Ia)
|
|
|
|
|
ENCODING("offset16_16", ENCODING_Ia)
|
|
|
|
|
ENCODING("offset16_32", ENCODING_Ia)
|
|
|
|
|
ENCODING("offset32_8", ENCODING_Ia)
|
|
|
|
|
ENCODING("offset32_16", ENCODING_Ia)
|
|
|
|
|
ENCODING("offset32_32", ENCODING_Ia)
|
|
|
|
|
ENCODING("offset32_64", ENCODING_Ia)
|
|
|
|
|
ENCODING("offset64_8", ENCODING_Ia)
|
|
|
|
|
ENCODING("offset64_16", ENCODING_Ia)
|
|
|
|
|
ENCODING("offset64_32", ENCODING_Ia)
|
|
|
|
|
ENCODING("offset64_64", ENCODING_Ia)
|
2014-11-24 04:08:18 -05:00
|
|
|
ENCODING("srcidx8", ENCODING_SI)
|
|
|
|
|
ENCODING("srcidx16", ENCODING_SI)
|
|
|
|
|
ENCODING("srcidx32", ENCODING_SI)
|
|
|
|
|
ENCODING("srcidx64", ENCODING_SI)
|
|
|
|
|
ENCODING("dstidx8", ENCODING_DI)
|
|
|
|
|
ENCODING("dstidx16", ENCODING_DI)
|
|
|
|
|
ENCODING("dstidx32", ENCODING_DI)
|
|
|
|
|
ENCODING("dstidx64", ENCODING_DI)
|
2010-01-01 05:31:22 -05:00
|
|
|
errs() << "Unhandled relocation encoding " << s << "\n";
|
|
|
|
|
llvm_unreachable("Unhandled relocation encoding");
|
|
|
|
|
}
|
|
|
|
|
|
2014-11-24 04:08:18 -05:00
|
|
|
OperandEncoding
|
|
|
|
|
RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s,
|
|
|
|
|
uint8_t OpSize) {
|
2010-01-01 05:31:22 -05:00
|
|
|
ENCODING("GR32", ENCODING_Rv)
|
|
|
|
|
ENCODING("GR64", ENCODING_RO)
|
|
|
|
|
ENCODING("GR16", ENCODING_Rv)
|
|
|
|
|
ENCODING("GR8", ENCODING_RB)
|
|
|
|
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errs() << "Unhandled opcode modifier encoding " << s << "\n";
|
|
|
|
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llvm_unreachable("Unhandled opcode modifier encoding");
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}
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#undef ENCODING
|
