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f00f521e9c
IBM power architecture has L1 cache line size equal to 128. Take advantage of that on that architecture, do not force more common value of 64. When it is possible to detect higher value, use that value instead. Keep the default to be 64.
45 lines
1.1 KiB
C
45 lines
1.1 KiB
C
/*
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* Copyright (C) Internet Systems Consortium, Inc. ("ISC")
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*
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* SPDX-License-Identifier: MPL-2.0
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*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, you can obtain one at https://mozilla.org/MPL/2.0/.
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*
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* See the COPYRIGHT file distributed with this work for additional
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* information regarding copyright ownership.
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*/
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#pragma once
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/*! \file isc/os.h */
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#include <isc/lang.h>
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#include <isc/types.h>
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ISC_LANG_BEGINDECLS
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/*%<
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* Hardcode the L1 cacheline size of the CPU to 64, this is checked in
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* the os.c library constructor if operating system provide means to
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* get the L1 cacheline size using sysconf().
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*/
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#define ISC_OS_CACHELINE_SIZE 64
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unsigned int
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isc_os_ncpus(void);
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/*%<
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* Return the number of CPUs available on the system, or 1 if this cannot
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* be determined.
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*/
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unsigned long
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isc_os_cacheline(void);
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/*%<
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* Return L1 caheline size of the CPU.
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* If L1 cache is greater than ISC_OS_CACHELINE_SIZE, ensure it is used
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* instead of constant. Is common on ppc64le architecture.
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*/
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ISC_LANG_ENDDECLS
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