From 8537adef4c1bff5b7fcc1d1b425d82fcbecf3659 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Sur=C3=BD?= Date: Fri, 27 Jul 2018 14:17:09 +0200 Subject: [PATCH 1/2] The isc_refcount_decrement must use memory_order_release and isc_refcount_destroy must run thread barrier with memory_order_require --- lib/isc/include/isc/refcount.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/isc/include/isc/refcount.h b/lib/isc/include/isc/refcount.h index 80ee9751ae..09d6af0a98 100644 --- a/lib/isc/include/isc/refcount.h +++ b/lib/isc/include/isc/refcount.h @@ -53,7 +53,7 @@ typedef atomic_uint_fast32_t isc_refcount_t; */ #define isc_refcount_current(target) \ - (uint_fast32_t)atomic_load_explicit(target, memory_order_relaxed) + (uint_fast32_t)atomic_load_explicit(target, memory_order_acquire) /** \def isc_refcount_destroy(ref) * \brief a destructor that makes sure that all references were cleared. @@ -85,6 +85,6 @@ typedef atomic_uint_fast32_t isc_refcount_t; * \returns previous value of reference counter. */ #define isc_refcount_decrement(target) \ - atomic_fetch_sub_explicit(target, 1, memory_order_relaxed) + atomic_fetch_sub_explicit(target, 1, memory_order_release) ISC_LANG_ENDDECLS From 953a957dfa1b9e6a024eca29fab0158053161fbb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ond=C5=99ej=20Sur=C3=BD?= Date: Wed, 5 Dec 2018 14:16:41 +0100 Subject: [PATCH 2/2] Just #define isc_refcount_increment0() to isc_refcount_increment() --- lib/isc/include/isc/refcount.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/isc/include/isc/refcount.h b/lib/isc/include/isc/refcount.h index 09d6af0a98..4e7f4d439f 100644 --- a/lib/isc/include/isc/refcount.h +++ b/lib/isc/include/isc/refcount.h @@ -69,7 +69,7 @@ typedef atomic_uint_fast32_t isc_refcount_t; * \returns previous value of reference counter. */ #define isc_refcount_increment0(target) \ - atomic_fetch_add_explicit(target, 1, memory_order_relaxed) + isc_refcount_increment(target) /** \def isc_refcount_increment(ref) * \brief increases reference counter by 1.