upstream/bind9
1
0
Fork 0
mirror of https://github.com/isc-projects/bind9.git synced 2026-06-11 07:40:00 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

silence comiler warning. [RT #18630]

Browse source
This commit is contained in:
Mark Andrews 2009-02-04 04:43:42 +00:00
parent 0b580e05ae
commit ba576cf8e7
1 changed files with 16 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

20
lib/isc/ia64/include/isc/atomic.h
View file

@ -14,7 +14,7 @@
* PERFORMANCE OF THIS SOFTWARE.
*/
/* $Id: atomic.h,v 1.4 2007/06/19 23:47:17 tbox Exp $ */
/* $Id: atomic.h,v 1.5 2009/02/04 04:43:42 marka Exp $ */
#ifndef ISC_ATOMIC_H
#define ISC_ATOMIC_H 1
@ -31,7 +31,11 @@
* (e.g., 1 and -1)?
*/
static inline isc_int32_t
isc_atomic_xadd(isc_int32_t *p, isc_int32_t val) {
isc_atomic_xadd(isc_int32_t *p, isc_int32_t val)
#ifdef __GNUC__
__attribute__ ((unused))
#endif
{
isc_int32_t prev, swapped;
for (prev = *(volatile isc_int32_t *)p; ; prev = swapped) {
@ -53,7 +57,11 @@ isc_atomic_xadd(isc_int32_t *p, isc_int32_t val) {
* This routine atomically stores the value 'val' in 'p'.
*/
static inline void
isc_atomic_store(isc_int32_t *p, isc_int32_t val) {
isc_atomic_store(isc_int32_t *p, isc_int32_t val)
#ifdef __GNUC__
__attribute__ ((unused))
#endif
{
__asm__ volatile(
"st4.rel %0=%1"
: "=m" (*p)
@ -68,7 +76,11 @@ isc_atomic_store(isc_int32_t *p, isc_int32_t val) {
* case.
*/
static inline isc_int32_t
isc_atomic_cmpxchg(isc_int32_t *p, isc_int32_t cmpval, isc_int32_t val) {
isc_atomic_cmpxchg(isc_int32_t *p, isc_int32_t cmpval, isc_int32_t val)
#ifdef __GNUC__
__attribute__ ((unused))
#endif
{
isc_int32_t ret;
__asm__ volatile(